The 65nm BCD (Bipolar-CMOS-DMOS) Power Management process node targets any type of power management chip up to 16V operation regardless of application and enables two advanced capabilities. First, it provides a new option to efficiently integrate heavy digital content with power management using high density digital libraries. Second, it enables a cost advantage through very low on-state resistance (Rdson) power transistors combined with the lowest number of production layers.
These advanced capabilities open the entire up to 16V operation power management market. This market size for PMICS up to 16V, is set to be about $9.4 billion for 2018, about 42 percent of the total power IC market, according to IHS Markit. The low voltage power management market includes most types of power products such as load switches, DC-DC converters, protection ICs, monitoring and driving ICs, and more. Most of these products include the power transistors in the chip (monolithic solution), and do not use external MOSFETs. These types of products are mostly cost sensitive with many players competing for the same socket.
However, with an aggressive Rdson of sub 1mΩ*mm², low production layers and 300mm wafer size, companies can gain multiple competitive advantages. The first is die size reduction. This reduction comes mainly from the low Rdson, but it also comes from the technology node using smaller size 5V CMOS transistors. Having smaller transistors also improves the efficiency of the product with smaller capacitance on the gate to drive. Second, the low number of mask layers is not only another enabler for additional cost benefits, but also provides a faster production cycle which is critical in more consumer electronics. Third, the usage of 300mm wafer size enables a better cost structure.