Monolithic solutions and digital integration
There is an increase in the digital content for power management applications (even the simple ones) to include more monitoring of parameters (such as over voltage, over current), more connectivity and smaller power solutions. For example, in the past three years, TowerJazz’s power management customers increased their digital content in power management ICs from around 10 percent to approximately 30 percent. The 65nm offers a digital density for the 5V digital library of 113kgate per square millimeter. This rises to around 800kgate per square millimeter for the 1.2V digital library.
As shown in the chart below, known as Chuck’s Hypothesis on future current density of power solutions developed by Charles (Chuck) Devries from Texas Instruments, the need for embedded digital, power and even external FET to a micro device in power management will continue and more power will be driven by a single IC to decrease the overall solution.
Graph of Chuck’s Hypothesis – More integration and smaller BOM showing increase in current per volume.
Higher power density requires higher switching frequencies to reduce the passive component size and to lower the EMI (Electro Magnetic Interference) in relevant parts of the electromagnetic spectrum. The increase in switching frequency above 1.8MHz reduces the EMI below this frequency and the conducted and radiated emissions are minimized in the strictly regulated AM band.
With 65nm LDMOS, a low Qgd is also achieved, allowing greater levels of integration and reduction in solution size which reduces parasitic components. Size reduction also helps reduce board design issues by allowing the power IC to be closer to the load and reduce board parasitic issues.
Examples of products that benefit from the 65nm BCD process and the main requirements from the technology.
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