Flex Logix has ported its FPGA fabric blocks to a number of TSMC manufacturing processes and DARPA has said it will work with the EFLX embedded FPGA technology for use by any company or government agency designing integrated circuits for the US Government.
As part of the agreement, Flex Logix will make available EFLX arrays in the TSMC 16FFC process node from 2.5K to 122.5K LUTs so that these companies and agencies can reconfigure RTL at any point during the design process. Having this flexibility will enable chip designers to increase performance, reduce power and lower the size/weight of their critical systems.
"Chip development costs and lead times keep increasing and the ability to reconfigure RTL at any time can eliminate expensive chip spins, enable one chip to address many customers and applications, and extend the life of chips and systems," said Geoff Tate, CEO and co-founder of Flex Logix.
EFLX is available in two core sizes (100 and 2.5K) today on multiple mainstream foundry processes: TSMC40ULP, TSMC28HPM/HPC and TSMC16FF+; and now is in development for TSMC16FFC as well. EFLX can also be ported to any proprietary CMOS process as well for organizations with their own fabs.
EFLX is a digital architecture for development of embedded FPGAs for integration into SoCs, ASICs and MCUs of a wide range of sizes. The EFLX arrays are programmed using VHDL or Verilog; the EFLX compiler takes the output of a synthesis tool such as Synopsys Synplify and does packing, placement, routing, timing and bitstream generation. The bitstream when loaded into the array programs it to execute the desired RTL.
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