Hardware-assisted verification platform leverages Xilinx's 40nm node FPGAs

November 07, 2011 // By Julien Happich
EVE (Emulation & Verification Engineering) announced the ZeBu-Blade2 hardware-assisted verification platform, the company's first member of the ZeBu emulation family based on Xilinx Virtex6-LX760 FPGAs implemented at the 40nm node. Aimed at application specific integrated circuits (ASICs) and systems on chip (SoCs), the emulator offers design teams fast execution and attractive pricing for hardware/software integration ahead of silicon availability.

Offered in two versions, populated with either five or with nine LX760 FPGAs with design capacity of 18- or 32-million ASIC gates, ZeBu-Blade2 is a single user emulator that can handle more than 70% of current ASIC designs, per usage surveys conducted by EVE. It can be deployed in co-emulation with hardware description language (HDL), C, C++, or SystemC-based cycle-level or transaction-level testbenches, or in emulation with synthesizable testbenches and in-circuit-emulation (ICE) driven by target systems. ZeBu-Blade2 features easy setup, fast compilation and fast execution speed in both transaction-based co-emulation and ICE.

ZeBu-Blade2 is supported by a comprehensive set of debugging capabilities including three types of probes –– static, flexible and dynamic –– for optimal analysis, fast waveform generation, interactive read and write access of any memory, and read/force/release of any register. The entire state of the design can be dumped and overwritten in few seconds. Save and restore, SystemVerilog assertions support, and monitors/checkers through fast transactors strengthen ZeBu-Blade2’s debugging features. When the emulated design is driven by a target hardware system through ZeBu-Blade2’s Direct-ICE interface, which includes 600 non-multiplexed and voltage programmable I/O pins, full-speed debugging can be performed using the built-in logic analyzer. Static and programmable triggering functions can be created using any register or signal in the design.

ZeBu-Blade2 compiles register transfer level (RTL) designs with up to 16 asynchronous primary clocks and unlimited derived clocks using clock-tree routing algorithms that prevent timing violations. The software generates compiled FPGA bitstreams from RTL code in three hours or less using small PC farms.

As with the entire ZeBu family, ZeBu-Blade2 is assisted by a large verification intellectual property (VIP) catalog of memory models, fast hardware transactors for popular protocols, and speed-rate adapters. Custom transactors can be created through EVE’s ZEMI-3, a unique SystemVerilog behavioral compiler based on the DPI-C standard compatible with SCEMI 2.0.

ZeBu-Blade2 is offered in two configurations: Hardware Development Platforms (HDP) and Software Development Platforms