IMEC, Soitec stack device layers

July 12, 2018 // By Peter Clarke
Research institute IMEC and SOI wafer supplier Soitec have demonstrated the stacking of active device layers implemented in 300mm-diameter wafers in a process known as sequential 3D planar.

This vertical integration of sequentially process device layers, also named sequential-3D integration (S3D), is seen as a promising alternative to lateral scaling.

The most critical challenge of sequential-3D-integration is managing the thermal budget and to avoid degrading circuits and interconnects in the bottom device layer the top device layer has to be processed at temperatures below 525 degrees C. This challenge has been overcome by using junction-less transistors in the top layer, which decreases fabrication complexity and the need for high temperature processing.

The top-tier device was processed at a temperature below 525 degree C achieving good device performance without impact from layer transfer (SS = 72mV/dec, DIBL = 80mV/V, Ioff = 1pA/micron, Ion=220microA/micron at VDD=1V).

IMEC worked with Soitec's SmartCut technology which it uses in the production of SOI wafers. IMEC used the technique to transfer a thin layer of crystalline material from one substrate to the substrate that had already been processed with a layer of devices.

The technique promises to bring the 3D benefits of reduce interconnect distances and RC-induced delays while offering superior alignment accuracy to the use of through-silicon vias (TSVs).

"Demonstrating a good performance of the top-tier device using a low-temperature process is an important breakthrough in our aim to develop sequential 3D as a valid option to further increase power-performance-area-cost in advanced technology nodes beyond 5nm," said Anne Vandooren, senior researcher at IMEC, in a statement.

"Together we are leveraging the maturity of Soitec’s Smart Cut process, excellent quality and thickness control, and imec’s advanced device and integration know-how, to develop another method to meet the PPAC (Power, Performance, Area and Cost) in scaling," said Bich-yen Nguyen, senior fellow at Soitec, in the same statement.

Related links and articles:

www.imec.com

www.soitec.com

News articles:

IMEC presents 'n-over-p' complementary FET proposal

Leti, Soitec form substrate research center

IMEC, Unisantis develop vertical-transistor SRAM


s

Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.