The product is intended to ease the design of reliable analog and mixed-signal ICs for automotive, medical, industrial, and aerospace and defense applications. It allows the design to consider active life through aging.
The Legato Reliability Solution is based on the Spectre Accelerated Parallel Simulator and the Virtuoso custom IC design platform.
In this release, Cadence introduces a simulation engine to enable defect-oriented testing that allows designers to evaluate the ability to eliminate die with manufacturing defects and resulting test escapes that cause field failures. It can also be used to optimize wafer test and early customer experience with the tool indicates that it accelerates defect simulation by more than 100x, Cadence said.
Dynamic electro-thermal simulation allows designers to simulate the on-chip temperature rise and validate the operation of over temperature protection circuits.
In this release, Cadence is also enhancing aging analysis to include temperature and process variation. Cadence is also providing an aging model for device degradation in advanced nodes with FinFET transistors.
"Designers are faced with the challenge of designing across the entire lifecycle, including eliminating the test escapes that become field failures early in the life cycle, preventing thermal overstress from operating in extreme conditions like under the hood of a car, and designing for 15 years or more of operating lifetime," said Tom Beckley, Cadence senior vice president and general manager, custom IC and PCB Group.
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