Leti, CMP offer OxRAM multiproject wafer service

August 04, 2018 // By Peter Clarke
French research institute Leti and low-volume IC manufacturing service organization Circuits Multi Projet (CMP) are offering multiproject wafer runs for OxRAM embedded non-volatile memory devices on 200mm-diameter wafers.

Manufacturing is performed on a 200mm CMOS line at Leti in Grenoble, France.

Leti’s OxRAM is a backend of line (BEOL) non-volatile memory that in the new platform will be based on titanium-doped hafnium oxide active layers. It is thought that like many other resistive RAM (ReRAM) technologies it is based on metal ion and oxygen vacancy migration to make and break a filamentary conducting memory.

OxRAM non-volatile memory is a promising for embedded memory applications on advanced nodes such as microcontrollers, security products, AI accelerators and neuromorphic computing (see Three pillars for Leti's post-CMOS plan ).

Leti's Memory Advanced Demonstrator (MAD) platform is intended to allow exploration of memory performance from technology and design perspectives. It includes: STMicroelectronics HCMOS9A base wafers on a 130nm node including routing on metal layers M1 to M4. OxRAM memory module is implemented in higher metal layers on top. One level of interconnect (i.e. M5) plus pads are fabricated in Leti’s cleanroom. The MPW service includes material engineering and analysis, developing critical memory modules, evaluation of memory cells coupled with electrical tests, modeling and design techniques to comply with circuit design constraints. Libraries are provided with active and passive electro-optical components.

"CMP has a long experience providing smaller organizations with access to advanced manufacturing technologies, and there is very strong interest in the CMP community in designing and prototyping ICs using this process," said Jean-Christophe Crébier, director of CMP, in a statement issued by Leti.

Related links and articles:

www.leti.fr

www.mycmp.fr

News articles:

Three pillars for Leti's post-CMOS plan

Technology talk at IMEC Forum


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