IMEC, which works with core commercial partners in semiconductor research and is presenting a number of papers at the International Electron Devices Meeting (IEDM) in San Francisco, California, this week.
For the paper on 5nm embedded MRAM IMEC performed a design analysis using a silicon-verified compact model of a pMTJ made to be compatible with the 5nm node. The pMTJ has nominal access latency of less than 2.5ns and less than 7.1ns for read and write operations, respectively. The analysis shows that STT-MRAM meets numerous requirements for level-one through level-three caches in high-performance computing and offers significant energy gains over SRAM for both read and write accesses. It meets target clock frequencies of more than 100MHz while occupying 43.3 percent of the area of the SRAM macro.
IMEC performed a design-technology co-optimization (DTCO) to define the requirements and specifications for STT-MRAM cells at the 5nm node and concluded that a high-performance STT-MRAM bit cell with the MRAM pitch being twice the contacted gate pitch of 45nm is the preferred solution for last-level caches at 5nm. In a second step, a high-performance STT-MRAM cell was fabricated on 300mm Si wafers and the characteristics of the magnetic tunnel junction were measured experimentally.
Energy comparison between SRAM and STT-MRAM by cache size. STT-MRAM becomes more energy efficient compared to SRAM at 0.4MB for read, and 5MB for write operations. Source: IMEC.
An examination of the energy profile for both SRAM and STT-MRAM showed the researchers that there are two cross-over points that impact system energy consumption: when STT-MRAM read and write energy becomes lower than that of SRAM at 0.4Mbytes an 5Mbytes. This is due to the exponential increase of SRAM standby power with increasing memory capacity.