Phosphorous tipped as 2D 5nm transistor material

July 13, 2017 // By Peter Clarke
Researchers from nanoelectronics research institute IMEC (Leuven, Belgium) have shown how to optimize field effect transistors based on 2D materials high performance logic beyond the 10nm node.

The researchers worked with scientists from KU Leuven in Belgium and the University of Pisa in Italy and also presented guidelines on how to select 2D materials in a paper in Nature Scientific Reports.

The benefit of 2D materials, such as graphene, is that they physically constrain electrons in the plane of the material while creating enhanced mobility in that plane. The researchers proposed a sandwich structure based on black phosphorous that they claim could be used to extend Moore's Law beyond 5nm gate length.

Structure of 2D-material transistor and gate stacks. Source: IMEC.

Scaling of conventional bulk materials, such as silicon, gives rise to negative short-channel effects and chip manufacturers have moved from planar transistors to FinFETs to try and overcome these. FinFETs are now progressing to lateral nanowire transistors.

"2D materials, with the atomically-precise dimension control they enable, promise to become key materials for future innovations. With advancing R&D, we see opportunities emerging in domains such as photonics, optoelectronics, biosensing, energy storage, photovoltaics, and also transistor scaling. Many of these concepts have already been demonstrated in the labs," said Iuliana Radu, distinguished member of technical staff at IMEC.

The work was supported by IMEC's chip company partners GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions and TSMC, and by the European Graphene Flagship project.

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Scientific Reports article

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