Startup launches analog IP from digital tools

January 31, 2018 // By Peter Clarke
Movellus Inc. (San Jose, Calif.) has launched itself on the market with a focus on the use of digital design and verification tools to implement analog circuit functionality.

The advantage of the approach is that because the functions are designed digitally time-to-market can be shorter and IP can be more easily ported to alternative process nodes or layer counts.

The company has launched a series of phase-locked loop (PLL) delay-locked loop (DLL) and low-voltage drop out (LDO) regulator generators.

It is not clear how the circuits compare with similar analog implementations in terms of performance, power consumption or area but the company claims that since its formation in April 2014 it has produced working silicon with multiple customers. These include semiconductor and systems companies working in artificial intelligence, networking, and FPGAs.

The PLL generator is available in TSMC 28nm HPC and Globalfoundries 14nm LPP process nodes. Meanwhile several FinFET process nodes are being prepared. The DLLs are designed to be robust against environmental and process variations and occupy 10,000 gates independent of the process technology while meeting a wide range of specifications, Movellus said.

The IP generators combine proprietary analog circuit architectures (RTL) with add-on software products that expand digital synthesis, static timing analysis, and place and route tools to create digital implementations of analog functions, Movellus said.

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