Thales is a multinational company that designs and builds electrical systems and provides services for the aerospace, defence, transportation and security markets.
A triple-modular-redundancy demonstrator has been designed to show how RISC-V can be used to build a flexible and extendible fault-tolerant voter CPU system mitigating Single Event Upset (SEU) with minimum impact on software.
The RISC-V cores at the heart of the demonstrator were developed using the Rocket Chip Generator, from University of California, Berkeley. The Chisel HDL is used for IP development and the RTOS is the Linux Foundation project Zephyr.
"Thales is looking forward to exploring possible applications of RISC-V in the space and other domains together with Antmicro. We view them as an important asset in the RISC-V ecosystem, joining the world of chip, FPGA and software development with a software-driven vision firmly grounded in open source," said Bertrand Tavernier, vice president of software technologies at Thales, in statement issued by Antmicro.
"We are thrilled to be among the first technology leaders working with Thales on bringing RISC-V to the wider Thales family, said Michael Gielda, vice president of business development at Antmicro, in the same a statement. "The fact that Thales is working with us to release the TMR RISC-V demonstrator and the related training materials on an open source license is an encouragement for the global industry to embrace the multifaceted technological advance that comes with the world switching to open standards on a level as fundamental as silicon."
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