Three pillars for Leti's post-CMOS plan

July 18, 2017 // By Peter Clarke
French research institute Leti has a post-CMOS plan that is driving research decisions. That plan rests on three broad pillars and some more specific developments such as neuromorphic and quantum computing.

Carlo Reita, director of technical marketing and strategy for nanoelectronics at Leti, explained the significance of the three pillars to eeNews Europe. And they are: novel devices, 3D stacking and novel computational architectures.

"One reason to research this is to support the high-performance computing mandate of our parent CEA. However, with 10MW data centers there is also an overwhelming need to reduce power consumption," said Reita. "IoT will have to go embedded with neural networks at 'leaf nodes' and power efficiency is important."

Roadmap links novel devices, 3D integration and novel computation. Source: Leti.

For now, fully-depleted silicon-on-insulator (FDSOI) is an important implementation technology. "About four years ago we let go of the FinFET and focused on planar FDSOI. Samsung has the 28nm FDSOI and Globalfoundries the 22nm and we're helping Globalfoundries move down to the 12nm node," Reita said.

However, in the medium term Reita sees the differences between FinFET and FDSOI diminishing as both branches of transistor manufacture evolve to stacked horizontal nanowires with gate-all-around at 7nm and beyond. "FDSOI can scale to the 10nm node; that is a 20nm pitch and 10nm gate length; but both branches will have their issues. There are a lot of electrostatic issues." There are also reportedly issues with device aging and robustness under operation.

And such problems with 2D scaling, or at least with the cost implications of such 2D scaling is one of the reasons Leti has pursued 3D integration for many years and has its own approach called CoolCube. Rieta admits that 3D stacking – apart from some specialized exceptions such as 3D-NAND flash memory – has yet to find commercial traction.

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