Toshiba takes 3D-NAND to 96-layers, 4 bits per cell

June 29, 2017 //By Peter Clarke
Toshiba has announced that it has developed a 4-bit per cell version of a 64-layer 3D-NAND flash memory and has produced a 96-layer version of a 3-bit per cell 3D-NAND. The company said it intends to combine the two in future high capacity devices.

The announcements serve to emphasize Toshiba Memory Corp.'s strong position in 3D-NAND flash memory even while the business is up for sale (see Toshiba backs Japanese group for memory business sale ).

Toshiba's QLC flash memory IC features a 64-layer stacked cell structure and achieves a memory capacity of 768Gbits/96Gbytes. Stacking 16 die in a package enables a 1.5Tbyte memory component, which Toshiba claims is the industry's largest capacity, and a 50 percent increase over Toshiba's previous multi-die memory (see Toshiba to sample terabyte memory in April ) based on 64-layer, 512Gbit ICs.

Such memories are destined for deployment in solid-state drives (SSDs) for use in datacenters but could eventually be used in enterprise and consumer SSDs, tablets and memory cards.

Samples of the QLC device began shipping in June to SSD and SSD controller vendors for evaluation and development purposes.

Meanwhile Toshiba has developed a 96-layer, 256Gbit/32Gbyte IC that is scheduled for release 2H17 with mass production is targeted for 2018. Toshiba reckons this IC is suitable for use enterprise and consumer SSDs, smartphones, tablets and memory cards. Going forward, Toshiba Memory Corporation will apply its 96-layer process technology to larger capacity products, such as 512Gbit/64Gbyte and 4-bit-per-cell technology, in the near future.

Related links and articles:

www.toshiba.co.jp

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