Achronix: Enhancing eFPGA with custom blocks

January 15, 2018 //By Achronix
Achronix: Enhancing eFPGA with custom blocks
This white paper looks at the use of Speedcore embedded FPGA to improve SoCs. It looks at the process of collaboration to define resource requirements and custom blocks giving examples of a neural network, a string search function, and high-speed packet processing. It also looks how the use of custom blocks can produce die array reductions compared with FPGA cores and standalone FPGAs. It also describes tool support for such design.
eFPGA, embedded

Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.