The JESD204 standard applies to analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). It is primarily intended to provide a common interface to FPGAs, but may also be used with ASICs designs.
As the resolution and speed of converters has increased, the demand for a more efficient interface has grown. The JESD204 interface brings this efficiency and offers several advantages over its CMOS and LVDS predecessors in terms of speed and size. Designs employing JESD204 enjoy the benefits of a faster interface to keep pace with the faster sampling rates of converters. In addition, there is a reduction in pin count, which leads to smaller package sizes and a lower number of trace routes that make board designs much easier.
The JESD204 standard is also easily scalable so it can be adapted to meet future needs. This has already been exhibited by revisions the standard has undergone. In fact, the JESD204 standard has seen two revisions since its introduction in 2006 and is now at revision B. As the standard has been adopted by an increasing number of converter vendors and users, as well as FPGA manufacturers, it has been refined, and new features have been added that have increased efficiency and ease of implementation.
What is JESD204B?
The original version of JESD204 was released in April 2006. The standard describes a multi-gigabit serial data link between converter(s) and the device(s) to which they are connected -- typically devices such as FPGAs or ASICs. In the first version of JESD204, the serial data link was defined for a single serial lane between a converter or multiple converters and a receiver. The lane is the physical interface between M number of converters and the receiver, which consists of a differential pair of interconnect utilizing current mode logic (CML) drivers and receivers. The link is the serialized data link that is established between the converter(s) and the receiver. The frame clock is routed