Advances within the JESD204B converter protocol: Page 2 of 9

December 16, 2013 //By Jonathan Harris & Ian Beavers, Analog Devices
Advances within the JESD204B converter protocol
A new converter interface is steadily picking up steam and looks to become the protocol of choice for future converters. This new interface, JESD204, was originally rolled out several years ago, but it has undergone revisions that are making it a much more attractive and efficient converter interface.
to both the converter(s) and the receiver and provides the clock for the JESD204 link between the devices.

Although both the original JESD204 standard and the revised JESD204A standard were higher performance than legacy interfaces, they were still lacking a key element. This missing element was deterministic latency in the serialized data on the link. When dealing with a converter, it is important to know the timing relationship between the sampled signal and its digital representation in order to properly recreate the sampled signal in the analog domain once the signal has been received (this situation is, of course for an ADC, a similar situation is true for a DAC). This timing relationship is affected by the latency of the converter, which is defined for an ADC as the number of clock cycles between the instant of the sampling edge of the input signal until the time that its digital representation is present at the converter's outputs. Similarly, in a DAC, the latency is defined as the number of clock cycles between the time the digital signal is clocked into the DAC until the analog output begins changing.

In the JESD204 and JESD204A standards, there were no defined capabilities that would deterministically set the latency of the converter and its serialized digital inputs/outputs. In addition, converters were continuing to increase in both speed and resolution. These factors led to the introduction of the second revision of the standard, JESD204B.

In July 2011, the second and current revision of the standard, JESD204B, was released. One of the key components of the revised standard was the addition of provisions to achieve deterministic latency. In addition, the data rates supported were pushed up to 12.5 Gbit/s, broken down into different speed grades of devices. This revision of the standard calls for the transition from using the frame clock as the main clock source to using the device clock as the main clock source.

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