High-level representation of a JESD204B system.
In the previous two versions of the JESD204 standard, there were no provisions defined to ensure deterministic latency through the interface. The JESD204B revision remedies this issue by providing a mechanism to ensure that, from power-up cycle to power-up cycle and across link re-synchronization events, the latency should be repeatable and deterministic. One way this is accomplished is by initiating the initial lane alignment sequence in the converter(s) simultaneously across all lanes at a well defined moment in time by using an input signal called SYNC~.
Another implementation is to use the SYSREF signal, which is a newly defined signal for JESD204B. The SYSREF signal acts as the master timing reference and aligns all the internal dividers from device clocks as well as the local multi-frame clocks in each transmitter and receiver. This helps to ensure deterministic latency through the system. The JESD204B specification calls out three device sub-classes: Sub-class 0 (no support for deterministic latency), Sub-class 1 (deterministic latency using SYSREF), and Sub-class 2 (deterministic latency using SYNC~). Sub-class 0 can simply be compared to a JESD204A link. Sub-class 1 is primarily intended for converters operating at or above 500 MSPS, but it can be used on converters operating below 500 MSPS to achieve greater timing resolution. Sub-class 2 is primarily for converters operating below 500 MSPS.
In addition to the deterministic latency, the JESD204B version increases the supported lane data rates to 12.5 Gbit/s and divides devices into three different speed grades. The source and load impedance is the same for all three speed grades being defined as 100Ω ±20%. The first speed grade in JESD204B aligns with the lane data rates from the JESD204 and JESD204A versions of the standard and defines the electrical interface for lane data rates up