Advances within the JESD204B converter protocol: Page 4 of 9

December 16, 2013 //By Jonathan Harris & Ian Beavers, Analog Devices
Advances within the JESD204B converter protocol
A new converter interface is steadily picking up steam and looks to become the protocol of choice for future converters. This new interface, JESD204, was originally rolled out several years ago, but it has undergone revisions that are making it a much more attractive and efficient converter interface.
to 3.125 Gbit/s. The second speed grade defines the electrical interface for lane data rates up to 6.375 Gbit/s. This speed grade lowers the minimum differential voltage level to 400 mV peak-to-peak, down from 500 mV peak-to-peak for the first speed grade. The third speed grade defines the electrical interface for lane data rates up to 12.5 Gbit/s. This speed grade lowers the minimum differential voltage level required for the electrical interface to 360 mV peak-to-peak. As the lane data rates increase for the speed grades, the minimum required differential voltage level is reduced to make physical implementation easier by reducing required slew rates in the drivers.

To allow for more flexibility, the JESD204B revision transitions from the frame clock to the device clock. Previously, in the JESD204 and JESD204A revisions, the frame clock was the absolute timing reference in the JESD204 system. Typically, the frame clock and the sampling clock of the converter(s) were the same. This did not offer a lot of flexibility and could cause undesired complexity in system design when attempting to route this same signal to multiple devices and account for any skew between the different routing paths. In JESD204B, the device clock is the timing reference for each element in the JESD204 system. Each converter and receiver receives its respective device clock from a clock generator circuit, which is responsible for generating all device clocks from a common source. This allows for more flexibility in the system design, but requires that the relationship between the frame clock and device clock be specified for a given device.

Space savings

The number of pins required for the same given converter resolution and sample rate is also considerably less. The table shown below provides an illustration of the pin counts for the three different interfaces using a 250 MSPS converter with various channel counts and bit resolutions. The data assumes a synchronization clock for each channel's data

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