To allow for more flexibility, the JESD204B revision transitions from the frame clock to the device clock. Previously, in the JESD204 and JESD204A revisions, the frame clock was the absolute timing reference in the JESD204 system. Typically, the frame clock and the sampling clock of the converter(s) were the same. This did not offer a lot of flexibility and could cause undesired complexity in system design when attempting to route this same signal to multiple devices and account for any skew between the different routing paths. In JESD204B, the device clock is the timing reference for each element in the JESD204 system. Each converter and receiver receives its respective device clock from a clock generator circuit, which is responsible for generating all device clocks from a common source. This allows for more flexibility in the system design, but requires that the relationship between the frame clock and device clock be specified for a given device.
The number of pins required for the same given converter resolution and sample rate is also considerably less. The table shown below provides an illustration of the pin counts for the three different interfaces using a 250 MSPS converter with various channel counts and bit resolutions. The data assumes a synchronization clock for each channel's data