Advances within the JESD204B converter protocol: Page 5 of 9

December 16, 2013 //By Jonathan Harris & Ian Beavers, Analog Devices
Advances within the JESD204B converter protocol
A new converter interface is steadily picking up steam and looks to become the protocol of choice for future converters. This new interface, JESD204, was originally rolled out several years ago, but it has undergone revisions that are making it a much more attractive and efficient converter interface.
in the case of the CMOS and LVDS outputs, and a maximum data rate of 5.0 Gbit/s for JESD204B data transfer using the CML outputs. Even with a limitation imposed on the JESD204B lane rate, the number of pins required is much less for the case of the JESD204B implementation. The motivation for the progression to JESD204B using CML drivers is quite obvious when looking at this table and observing the dramatic reduction in pin count that can be achieved.

Pin count comparison for a 250 MSPS, 14-bit ADC.

To help further illustrate the advantages of moving from LVDS to JESD204B, the image below shows the reduction in layout complexity for the JESD204B outputs. The example shows two 14-bit, dual-channel, 250 MSPS ADCs -- the AD9643 and the AD9250. In the case of the AD9643 (left) there are 30 output lines routed for the digital outputs (one synchronization clock is sent for both channels in this case). By comparison, in the case of the AD9250 (right) there are four output lines routed for the digital outputs.

Comparison of dual 14-bit 250 MSPS ADC layout: LVDS (left) versus JESD204B (right).

As can be seen, the LVDS lines on the AD9643 evaluation board must be carefully routed such that all the lengths are carefully matched to avoid timing issues in the FPGA where the data is received. This makes the output routing more complex and tedious. However, in the case of the AD9250 evaluation board, the output lines for the JESD204B CML outputs are quite simple to route since there are only four to be concerned with. This helps further illustrate the advantages of moving to JESD204B.

JESD204B device configuration flexibility

Although converters may have JESD204B serial lanes defined by a number, letter, or other nomenclature to designate their particular relevance in the complete link, they are not required to be fixed. The specification allows for re-mapping of these assignments in the

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