Pin count comparison for a 250 MSPS, 14-bit ADC.
To help further illustrate the advantages of moving from LVDS to JESD204B, the image below shows the reduction in layout complexity for the JESD204B outputs. The example shows two 14-bit, dual-channel, 250 MSPS ADCs -- the AD9643 and the AD9250. In the case of the AD9643 (left) there are 30 output lines routed for the digital outputs (one synchronization clock is sent for both channels in this case). By comparison, in the case of the AD9250 (right) there are four output lines routed for the digital outputs.
Comparison of dual 14-bit 250 MSPS ADC layout: LVDS (left) versus JESD204B (right).
As can be seen, the LVDS lines on the AD9643 evaluation board must be carefully routed such that all the lengths are carefully matched to avoid timing issues in the FPGA where the data is received. This makes the output routing more complex and tedious. However, in the case of the AD9250 evaluation board, the output lines for the JESD204B CML outputs are quite simple to route since there are only four to be concerned with. This helps further illustrate the advantages of moving to JESD204B.
JESD204B device configuration flexibility
Although converters may have JESD204B serial lanes defined by a number, letter, or other nomenclature to designate their particular relevance in the complete link, they are not required to be fixed. The specification allows for re-mapping of these assignments in the