While it is an optional feature that the specifications allow, if an ADC vendor has a cross-bar mux feature to reassign logical to physical output assignments, then the link I/O can be reconfigured in the best order for the easiest layout. The FPGA receiver can take the same initial configuration data and change the expected lane assignments to recover the data. With this ability, the routing of lanes from one device to the other can be made much easier and independent of the initial named assignment by the silicon vendor in the datasheet.
The differential impedance of each trace pair should be 100Ω, with a termination of 100Ω at the receiver. It's also important not to neglect impedance discontinuities at interconnects and to maintain a near 100Ω differential transmission line over connectors. In general, system layout should aim to minimize signal loss on the JESD204B link and adhere to the interconnect insertion loss mask in the specification for the particular application baud rate. Also, an AC-coupled approach is suggested to mitigate mismatches in common-mode voltages at the transmit and receive devices.
While the physical layer (PHY) is characterized at the component pin level by the converter and FPGA providers, what design engineers really want to know is how well the PHY layer works in their particular system. A new FPGA software eye scan tool called Analog Devices Linux JESD204B Eyescan software – that was developed by Analog Devices and Xilinx – is now available to identify that detail. The JESD204B receiver can provide additional adaptive gain control (AGC) and equalization (EQ) to amplify the high-frequency component of the