JESD204B physical layer evaluation.
Each JESD204B differential lane should be matched in length intra-pair between the +/- signals. While lane-to-lane, or inter-pair, length matching is not critical, matched lengths within a pair are still important. Any intra-pair trace mismatch will close down the available data eye seen at the receiver, effectively limiting the bandwidth of the link.
The JESD204B PHY of an ADC or DAC can be modeled using what is known as an IBIS-AMI (I/O Buffer Information Specification-Algorithmic Modeling Interface) model. IBIS-AMI not only provides the I/O characteristics of the pin, it also offers a way to simulate the behavioral algorithm of the PHY layer. With this capability, system designers can measure the impact of jitter, rise/fall times, pre-emphasis, and equalization within the signal path of their systems.
This type of model provides several advantages for system designers. It's interoperable with many advanced simulation packages, so models from different semiconductor vendors can be run together to simulate both ends of a link. Users can set the silicon control parameters in the IBIS-AMI model as needed for their system and even simulate a matrix of options to find the best-case profile. And with the model's efficient performance, multimillion-point simulations can be run in a matter of minutes.
JESD204B calls for some mandatory test patterns to be made available on the link by the transmitter. These patterns are necessary to be able to validate the data integrity of the serial interface. One set of patterns