The need for ultralow-power ADCs
Today’s wireless electronic systems store and process information in the digital domain. For these systems to interface with real-world signals, conversions between the analog and digital signals are required. Therefore, one of the keys to the success of these wireless systems has been the advance in analog-to-digital convertors (or ADCs). To be applicable for wireless standards, such as the 802.15.14g, the ADCs have to meet some stringent requirements: they need to be low power, have a high conversion rate (expressed in mega-samples per second or MS/s) and a high resolution (>10 bits). This resolution indicates the number of discrete values the ADC can produce over the entire range of analog values. Since the values are stored in binary form, the resolution is expressed in bits.
DAC matching, a challenge for accurate designs
Among the many ways of implementing an ADC, the SAR or successive approximation ADC is attractive because of its excellent power efficiency. A SAR ADC uses a comparator to successively narrow down the range that contains the input voltage. A key component in the design of the SAR ADC is an internal digital-to-analog convertor (or DAC) which drives the comparator. But the role of this DAC is also critical, since the accuracy of the SAR ADC is mainly defined by the DAC capacitor matching. This matching is mainly influenced by manufacturing processes and physical design. In modern CMOS technologies, the intrinsic accuracy of the SAR ADC is therefore limited to 10 to 12 bits.
Researchers look for solutions to improve the DAC matching. One way is to scale up the device dimensions, but this is at the expense of power efficiency and speed. Alternatively, calibrations are introduced to correct the circuit imperfections by measuring and correcting the induced errors. These calibrations are mostly implemented off-chip, since the power for the calibration circuit is relatively high when implemented on chip.