DC Accurate Driver for 20-Bit SAR ADC Achieves 2ppm Linearity

February 09, 2015 //By Guy Hoover, Linear Technology
DC Accurate Driver for 20-Bit SAR ADC Achieves 2ppm Linearity
As resolution and sample rates continue to rise for analog-to-digital converters (ADCs), the driver circuitry for the ADC analog input, not the ADC itself, has increasingly become the limiting factor in determining overall circuit accuracy. First, the driver circuitry must buffer the input signal and provide gain. In addition, it must level shift or convert a single-ended signal to a fully differential signal to satisfy the input voltage range and common mode requirements of the ADC. All must be done without adding distortion to the original signal.

This article presents a simple ADC driver circuit that converts a ±10V single-ended input signal into a fully differential signal capable of driving the LTC2377-20 20-bit SAR ADC with a combined linearity error of only 2ppm. Options for providing higher input impedance and a lower overall supply current are also examined.


The circuit of Figure 1 converts a ±10V single-ended signal into the ±5V fully differential signal required by the LTC2377-20 (U1). The LTC2377-20 is a 20-bit, 500ksps, low power SAR ADC with a typical integral nonlinearity (INL) of ±0.5ppm. The voltage at AIN is buffered by U4, which in turn drives the U5 resistor string, acting as a precision divider. U3 operates in a gain of minus one-half and drives the center of the U5 resistor string to maintain the ADC common mode voltage at VREF/2.

Figure 1. ±10V input range, 20-bit, 500ksps data acquisition system with 2ppm INL. For full resolution click here.

U3 and U4 are LT1468A low offset highly linear op amps. U5 is a LT5400A quad matched resistor network with a guaranteed maximum mismatch of 0.01%. Matched resistor values in U5 are important because any mismatch contributes to both offset and full-scale error in this circuit. For this reason and because of their extremely low voltage coefficient, do not use discrete resistors instead of the LT5400A. R4 provides a quarter-scale shift to the output of U3. R1 and R2 form a divider that biases the noninverting input of U3 at VREF/2.

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