Eight ways to improve RF spurious performance

February 28, 2012 //By Pete Hanish
Eight ways to improve RF spurious performance
Pete Hanish, Applications Engineer, Texas Instruments examines a number of ways to improve RF spurious performance

RF board design is as much about keeping signals out of the places they don't belong as it is about getting signals to the places they do belong. It requires conscious effort to keep signals isolated to their intended portion of the signal path. Tones, signals, clocks, and all of their harmonic products generated anywhere on the board have a tendency to sneak into output signals as spurs, or worse, into mixers and converters where they get shifted, reflected, and aliased into spurs. Transmit mask requirements mean that even the tiniest spurs can block release of a product.

The importance of spur reduction is compounded by today’s trend towards software-defined radio (SDR) enabled by wideband devices. Because a single platform design can be deployed to address multiple frequency bands, plug-in RF modules are being displaced by larger boards where more signals can interfere with each other. Small plug-in RF modules, including most RF vendor evaluation modules, are completely isolated and exhibit extraordinary spur performance, but use special design techniques. Myriad vias, topside routing, dedicated ground planes, and other layout techniques that work brilliantly for small RF boards often do not scale well.

Low spur RF layout often depends on the intuition of an RF engineer, because layout tools are optimized for large scale layout, not electromagnetic analysis. Usually basic rules are applied during layout and board review, but the real test only comes around once a board has been prototyped and is under evaluation in the lab. After basic board functions, such as power level and linearity, have been checked, evaluation of spurious performance becomes the focus. At this late stage, spurs require the RF engineer, who works the "black magic" to identify a root cause and a fix. Not only is such debug time nearly impossible to predict and schedule, but the fix often involves a board spin, which incurs project delay and expense.

Most of the RF engineer's

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