Packaging advances and power converter miniaturisation

March 20, 2014 //By Doug Ping
Packaging advances and power converter miniaturisation
Doug Ping, Principal Application Engineer, Vicor examines  how packaging advances are matching semiconductor progress in power converter miniaturisation.

Today's electronic systems, especially those in areas such as telecommunications infrastructure, networking and data management, pack ever-more functionality into smaller and smaller profiles. The microprocessors and other highly-integrated ICs on which they are based require correspondingly greater levels of power, often at voltages that are lower, and currents that are higher, than ever before.

Power provision has evolved along with every other component and subsystem: regulation, distribution and voltage conversion have had to migrate on to the main system circuit boards and can no longer be designed as a separate entity. Advanced packaging designs shrink power-conversion functions enabling greater power integration with main board functions; dramatically improved efficiencies cuts losses to levels that make heat removal from those smaller packages, a practical endeavour.

Many of the trends in today's systems were evident as long ago as the early 1980s – a convenient point in the context of this article, as it marks the period during which linear power supply topologies were being replaced by switching methodologies for the great majority of designs – and also saw the appearance of the “brick”, of which, more later. State-of-the-art design rules for chip fabrication were around 1.5 microns; parts already fabricated that you bought off the shelf, would likely be larger still. The change of semiconductor geometries that Moore's Law has charted, from 1.5 microns to today's leading-edge 22 nm, represents an increase in functional density of over 4600:1.

Figure 1: In three decades, commercial semiconductor processes for fabricating digital circuits have moved from the 1.5 μm node to the 22 nm node, shown here on a logarithmic scale (left).

Reduced silicon geometries drove integration, packing more and more functional blocks on to each chip. Beyond that, the chip integration story is largely one of packaging. The economically-optimal die size has not changed much – other than in the case of the largest and fastest processors, FPGAs and systems-on-chip. But compare an earlier-generation 40-pin DIP with today’s chip-scale-package, micro-BGA offering and the trend is clear to see.

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