Problems and pitfalls with signal integrity at 10 Gbits/sec and beyond

September 26, 2011 //By Kinana Hussain
Problems and pitfalls with signal integrity at 10 Gbits/sec and beyond
Kinana Hussain of Vitesse Semiconductor Corp., looks at how those initiating their first designs in the 10-Gbits/sec realm must confront signal-quality issues as backplanes and network interfaces move into that speed range.

Experienced designers of 10 Gbits/sec (10G) Ethernet, SONET/OTN, Infiniband (QDR/FDR), and Fibre channel (16/8GFC) products are well aware that the maintenance of signal quality is far more difficult at 10-Gbits/sec speeds than in the 1-to-3 Gbits/sec range. Those who are initiating their first designs in the 10-Gbits/sec realm may have to confront new realities that will dominate signal-quality issues, as backplanes and network interfaces move into that speed range.

There are discontinuities which are encountered, not only at the level of the individual device, but also at the level of the board trace, and these influence both board layout and the choice of substrate materials (such as FR4). A properly shaped, “clean” transmit signal will look very different at the receiver, as an eye pattern shows, Figure 1 .

 

Figure 1: Eye pattern clearly shows the signal degradation between transmitted signal shape and received signal shape, which occurs to signal path attributes.

Characterizing signal-integrity issues for line cards and backplanes at 10 Gbits/sec and above requires visualizing the design at board level and device level simultaneously, Figure 2 .

 

Figure 2: Proper equalization can successfully restore degradation buildup, which occurs at successive stages of the signal path.

In fact, even though system developers must keep track of the equalization and error-correction capabilities of individual devices used in high-speed designs, printed circuit board (PCB) designers have been called the “gatekeepers” of 10G design methodologies. When the task is considered at both board and device levels at once, a few common sources of potential signal integrity problems emerge:

PCB Layout: Characteristics of physical design, such as the use of via stubs, can have a significant impact on the integrity of data channels operating at tens of gigabits per second. AC-coupling difficulties can be aggravated by the scrambling methods used in advanced designs. As standards have shifted from 8B/10B encoding to 66B/64B, such scrambling is an order-of-magnitude more difficult to address.

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