(Editor's note : Click here for a complete, linked list of all previous installments of the series.)
This article addresses the impact of clock jitter on high-speed link performance. In Part 1 , we provided foundational concepts of high-speed communications links. In Part 2, we discuss the basics of jitter budgeting.
Standards that convey increasingly large amounts of data over greater distances are constantly being developed. Committees and standards bodies comprising engineers from various interests establish jitter budgets based on the goals of the standard being developed (throughput and distance); while taking into account the limitations of the blocks that make up the communications link.
Figure 1 shows a typical high-speed communications link incorporating an embedded clock. Each subsystem (clock, transmitter, channel, and receiver) contributes to the overall jitter budget. Subsystem jitter includes a deterministic (DJ) and a random component (RJ) as shown in the Figure.
In order for acceptable (note 1) communication to occur, the following condition must be satisfied, Equation 1 :
TJSYS(BER) ≤ 1 UI
TJSYS is the total jitter and
1UI is one unit interval (period of one bit)
Total jitter (TJ) includes the sum of deterministic and random jitter of each subsystem. Due to the nature of the random jitter, this summation requires special attention. Random jitter exhibits a Gaussian (random) distribution and is unbounded.
Therefore, random jitter is expressed as an RMS value and is evaluated within a specific bandwidth of measurement/integration. For example, the jitter measurement bandwidth of the receiver shown in Figure 1 is f2 - f1 (see Figure 2 ). This is because the receiver phase-locked loop (PLL) tracks jitter below f1 (thereby rejecting it), and the upper frequency limit of the transmit PLL is f2. From the receiver’s perspective, random noise that would degrade link performance falls between these limits.