SIGNAL CHAIN BASICS #71: How supply noise impacts clocking devices

November 15, 2012 //By Dean Banerjee
SIGNAL CHAIN BASICS #71: How supply noise impacts clocking devices
Dean Banerjee, Applications Engineer, Texas Instruments examines how supply noise impacts on clocking devices.


Supply noise can degrade the random jitter performance of clocking devices. Random jitter is calculated from phase noise (L), offset frequency (f), and clock frequency (Fclk) (Equation 1):

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 Equation 1

Typically, L(f) is the clock’s phase noise, but also could mean the spurs and phase noise on the clock as a result of supply noise. It is the noise and spurs near the clock frequency that cause jitter degradation. For instance, if there is 10 kHz supply noise onto a 100 MHz clock, it is not 10 kHz spurs, but rather the spurs at 100 MHz +/– 10 kHz that cause jitter degradation.

To understand supply noise impact in general, first examine the impact of a sinusoidal noise source using Equation 2:


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 Equation 2
Once the impact of this supply noise is understood for an arbitrary frequency, f, this can be expanded to any spectrum of power supply noise. By understanding how the noise source (Equation 2) impacts a clocking device’s most noise-sensitive blocks, and how they are shaped by the phase-locked loop (PLL), the resulting impact on jitter can be found.
Supply noise impact on an oscillator

Oscillators such as VCOs, VCXOs, XOs, OCXOs, and TCXOs can be considered for the purpose of supply noise discussions. Their supply noise sensitivity can be characterized with the supply pushing constant, KPUSH , as the frequency for a given change in supply voltage.

The noise source in Equation 2 produces sidebands at frequencies equal to Fclk +/– f. The amplitude of these sidebands can be calculated using Equation 3.

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 Equation 3
β is the modulation index and calculated by traditional FM modulation theory (Equation 4).

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Equation 4

Depending on whether the oscillator is free-running, driving a

Design category: 

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