In a world where Application Specific Integrated Circuits (ASICs) and Application Specific Standard Products (ASSPs) are dominating every conceivable application, greater attention is being applied to their long term reliability. These chips are being built on smaller lithographies, running at higher speeds, dissipating more power and to make things worse, they are being encapsulated in ever decreasing package sizes. What could possibly go wrong?
Plenty! Higher device performance comes at a price; higher temperatures. And with higher temperatures comes lower reliability if thermal considerations aren't carefully controlled. Semiconductor manufacturers have long been aware of the problems associated with heat.
Most have application notes and white papers plastered across their web sites espousing the benefits of careful calculation of power management using their values of ΘJA and ΘJC (Junction-to-Ambient and Junction-to-Case thermal resistance, respectively) often with sidebars suggesting various heat sinks to use in marginal situations. This puts the burden of solving temperature related problems on the backs of the user.
Recent technology advances and the proliferation of the use of Thermal Test Chips like those developed by JVD, Inc. for Thermal Engineering Associates of Santa Clara, CA is allowing semiconductor manufacturers and companies designing their own ASIC/ASSP devices to get ahead of the curve by thermally engineering their silicon before going to production.
Thermally Engineer Your Own ICs
Today, almost anyone can design a thermally engineered IC. Whether you’re a designer at a commercial semiconductor company or you’re crafting your own ASIC, the tools are readily available to physically simulate the thermal effects of your design, well in advance of spending any money to produce your first silicon prototypes. Thermal Test Chips (TTCs) allow system designers to fully model, measure and modify their designs before committing to costly silicon.
TTCs are special silicon die (yes, they are Analog ASICs) that are used to model and measure the thermal performance of your chip design in situ before you commit those tooling