Verification of SoC internal channel characterization using an ADC

September 17, 2013 //By Kushal Kamal and Siddi Jai Prakash
Verification of SoC internal channel characterization using an ADC
Kushal Kamal and Siddi Jai Prakash of Freescale outline the challenges and good design practice posed by the SoC design and verification stage.

A generic Nyquist Data Converter-based Analog to Digital Converter (ADC), based on a Successive Approximation Register (SAR) or Redundant Signed Digit (RSD) Algorithm, is shown in the block diagram in Figure 1. Industrial convention is to call an ADC based on a SAR Algorithm as a SAR ADC; the one based on RSD Algorithm as a Cyclic ADC. In the generic architecture of such ADCs there are two switches. One is called the Sampling Capacitor Switch and the other an ADC Switch. For an ADC to convert an analog signal to its corresponding digital word there are 2 phases: Sampling Phase and Conversion Phase.
 
Sampling Phase

In this phase the sampling capacitor switch is closed and the ADC Switch is open, as shown in Figure 1. As is evident, the ADC Driver is connected to the sampling capacitor via the sampling capacitor switch. The potential of the ADC driver is basically the voltage that the ADC would convert to a digital word after the end of sampling and conversion phases.

During the sampling phase the voltage of the ADC driver will be sampled on the sampling capacitor depending upon the source impedance (R) of the connection between the ADC driver and sampling capacitor and the capacitance value of the sampling capacitance (C). Basically the sampling time should be 5-10 times the RC values to sample the correct voltage on the sampling capacitor. Also the profile of the potential built on the sampling capacitor depends on the current drive strength of the ADC driver.

Sampling time is generally a few clock cycles. There are a couple of ways to alter the sampling time of the ADC. The number of clock cycles may increase/decrease or the frequency of clock can be changed (within ADC clock frequency range) and thus sampling time can be changed.

Figure 1: State of the ADC switches during the sampling phase

Conversion phase

Figure 2 shows the

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