Have you ever experienced unexpected droop when you’ve plotted out the frequency response of a signal processing system? When you expected that the frequency response would be flat (or at least accurate to the curve you designed to), but instead it rolls smoothly and lazily away from that target value, insulting you with its casual sogginess? If so, you’ve experienced the consequence of having a sinc() frequency response. You could say that you’ve had a clo-sinc-ounter – though possibly of a kind other than the third. Let’s look at what I mean by that.
This issue can crop up both at the input to and the output from a sampled data system. Let’s look at the output first. When you want to turn a stream of sample values back into an analog system, you apply those digital samples to a DAC. Now, most DAC ICs and modules have a ‘held’ output. That means that when they receive a new digital sample the output voltage changes promptly to the corresponding new value – and stays there, until the next sample comes along. This behavior is so commonplace that many engineers assume that it’s the norm and that the output voltage of such DACs somehow represents the sample stream correctly (apart from a bit of pesky high frequency noise).
This is not true. This 'hold' process causes the frequency response of such a system to differ from that of a system where the output voltage is only asserted very briefly at each sample instant. Such a spiky output voltage is hardly ever convenient in a real world application, which is why you rarely encounter it.
Stretching each sample’s voltage out to 'fill the space available' is an example of a zero order hold. The output frequency spectrum of such a system is equal to that of an ideal, spiky-output system multiplied by the spectrum of the rectangular impulse that fits between two