22nm FPGA maker takes on Xilinx and Altera
The Speedster 22i HD and HP product families are the first FPGAs to be built on Intel’s 22nm process technology using the new FinFET transistors and include fully integrated hard IP protocol functions targeted at communications applications. These include the entire I/O protocol stack for 10/40/100 Gigabit Ethernet, Interlaken, PCI Express Gen1, 2 and 3 and memory controllers for 2.133Gbps DDR3.
The first devices to ship are the high density synchronous HD family that provides up to 1.7 million effective LUTs (look up tables) and 144Mbits of embedded RAM. The high end device includes sixteen 28Gbps SerDes, sixty four 12.75Gbps SerDes and 960 general purpose 2.133Gbps I/O lines. The family is aimed at high-end switch and bridging applications.
The HD family is a departure for Achronix which used a self-timed design for its previous high speed FPGAs built in 65nm. Moving to a traditional clocked architecture with higher densities is a direct challenge to the high end, high margin parts from the two main competitors.
The 22nm technology gives a power advantage over the 28nm devices that are starting to ship, says Holt, with a typical power consumption of 24W for the largest devices, half that of 28nm devices, mainly from the integrated I/O blocks and static power advantage of the FinFET transistors.
“Part of our differentiating strategy is to integrate best-in-class, silicon-proven IP,” said John Lofton Holt, Achronix’s founder and Chairman of the Board. “For example, beyond the power and performance advantages afforded by Intel’s 22nm process, our Speedster22i devices also use an entire portfolio of industry-leading I/O, core and packaging IP that was developed by Intel. This helped us achieve previously unreachable levels of performance and signal integrity, and at the same time, reduce our development time and development costs.”
Achronix is still using its patented picoPIPE self-timed architecture for the HP family that operates at up to 1.5 GHz but with half the density, and are aimed at feed-forward data flow and DSP applications. The largest member of the HP family has 250 thousand LUTs and 64 megabits of embedded RAM.
Both the HD and HP families are supported in Achronix’s mature ACE design tools version 4.2 which is built on the Eclipse open source platform and run under both Windows and Linux operating systems. Additionally, Achronix provides HDL Synthesis tools from both Synopsys and Mentor as part of the ACE tool suite.
Engineering samples of the HD1000 will begin shipping in Q3 2012. The HD1000 is the industry’s largest FPGA with over 1 million effective LUTs and 84 Mb of embedded RAM. The remaining HD and HP devices will be rolled out in the following 12 months.