Accellera posts standard to track soft IP usage throughout chip design flow
Using the Soft IP Tagging 1.0 standard, engineers now have the ability to easily determine if a block of IP is contained within a chip, if it is the correct version, and if it is a candidate for reuse. In addition, semiconductor foundries, providers of IP, and manufacturers of design tools now have a standard way to track IP usage and royalty information with their customers.
The chip design process can include editing, synthesis, timing, placement, wiring, and other steps. Normally, control of a third-party IP source is lost once the block of IP is licensed, unlocked, or otherwise made available in clear code. IP Tagging 1.0 facilitates a data-driven method to tag a block of IP and track “where used” for applications such as ownership, royalty calculations, and recognition. It also facilitates the implementation of version identification for applicable bug fixes and errata and allows tracking of other data.
Kathy Werner, Accellera’s IP Tagging working group chair, commented, “Soft IP Tagging 1.0 not only provides a mechanism for version control and bug tracking, but can be used to determine the compatibility of an IP block for reuse in a future design. Engineers can now feel confident there is a standard methodology built around IP reuse, tracking, and data control.”