Advanced silicon, package, board co-design capabilities combined with on-demand EDA configuration

Advanced silicon, package, board co-design capabilities combined with on-demand EDA configuration

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Cadence Design Systems' latest version of Allegro PCB and IC packaging technology delivers new capabilities that the company says provide a significant increase in both productivity and predictability across silicon, SoC and system development. These include advanced miniaturization capabilities, uniquely integrated power delivery network analysis, DDR3 design-in kit, bolstered co-design features, and flexible team-design enablement to address global designer productivity.
By eeNews Europe

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The company also announced that the Allegro 16.5 technology will be available through product configuration that enables users to access advanced features on-demand for specific design tasks, thus optimizing total cost-of-ownership.
Assisting system developers, the Allegro 16.5 release provides many capabilities that enable a more productive, predictable path and closure to product creation.

New in this version of Allegro is a constraint-driven flow for embedded components that employs advanced miniaturization techniques used in state-of-the-art products to reach new levels of functional density. Traditionally, manual layout has been used to place and route embedded components, but this is an error-prone process with multiple iterations and no design rule checking.

The Allegro technology enables a simpler way to place and route these components with its constraint-driven approach. The new Allegro Power Delivery Network Analysis is seamlessly integrated with Allegro PCB Editor for comprehensive power trade-offs of fully routed PCBs. Increasing use of standards-based interfaces such as DDR4 and PCI Express 3.0 is making timing closure on PCBs extremely challenging.

The new PCB Interconnect Design Planning option uses a Cadence-patented hierarchical abstraction, coupled with semi-automatic approaches, that leverages feedback from the route engine to accelerate the path to timing closure.
The new concurrent team design authoring capability of Allegro also shortens the time it takes to create design intent by leveraging the power and skill of a distributed engineering team. 

Starting with Allegro 16.5, Cadence will extend SoC Realization by providing package-board-aware SoC IP. With this release, a package-board-aware DDR3 SoC IP methodology kit will be available to provide a compliant and fast implementation path from silicon IP to package and board. Similar support for other protocols, such as the recently announced DDR4 memory standard, will come in the future, according to Cadence. 

Allegro technology is built upon a unique silicon-package-board co-design approach, with direct bi-directional integration with flows from the Cadence Encounter Digital Implementation System and Virtuoso custom analog products lines, including low-power, mixed-signal, gigahertz, RF, and SiP/3D-IC flows.

Allegro products provide a scalable PCB and IC package design solution that leverages a constraint- and rules- driven methodology, from logical design authoring through physical implementation to signal and power integrity analysis and signoff.
Extending Silicon Realization, the new system-in-package (SiP) distributed co-design capability works with Encounter Digital Implementation System and Virtuoso custom analog technology to enable cross geographic, company and team design, reducing time to package-optimized chip tape-out. 

Visit Cadence at www.cadence.com

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