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An early look at the JEDEC JESD204B third-generation high-speed serial interface for data converters

Technology News |
By eeNews Europe

The JEDEC standards organization has published two versions of the JESD204 high-speed serial digital interface specification for data converters and logic devices.  The first revision, the JESD204 2006 specification, brought the advantages of SerDes-based high-speed serial (3.125 Gbps maximum) interfaces to data converters.  The second revision, the JESD204A 2008 specification, added critically important enhancements: the support for multiple data lanes and the support for lane synchronization.  Lane synchronization enables JESD204A to be used in quadrature (I/Q) sampling systems, the technology which underpins modern 3G, 3G+ and 4G broadband wireless communications.  See Figure 1.

Figure 1 – JESD204 (2006) versus JESD204A (2008)

A third revision of the specification, JESD204B, has been recently completed by an international JEDEC JC-16 Task Group (Project 150.01), comprising about 65 members from 25 companies (systems OEMs and semiconductor companies).  The published JESD204B specification from JEDEC is expected in 2H2011. JESD204B is expected to introduce three new enhancements that hold promise to drive this new interface into ubiquitous adoption by data acquisition system engineers worldwide.  These enhancements are: a higher maximum lane rate (higher bandwidth); support for deterministic latency through the interface; and support for harmonic frame clocking (or single clock architecture data converters).  See Table 1.

Table 1.  JESD204 Specification Evolution

There are numerous system design merits associated with JESD204A/B as compared to legacy parallel interfaces. Briefly, these benefits include a significant decrease in the number of higher-bandwidth interconnect PCB traces, which enables increased system reliability systems (most failures occur at points of interconnect); reduced PCB complexity, which impacts both NRE costs and marginal production costs as very often the system can be implemented using fewer PCB layers; and the opening up of a critical bottleneck in the digital signal processing bandwidth of the system design, which enables higher system performance.

Higher Lane Rate to Reduce IC Package, PCB Size and Cost

The JESD204A 2008 specification defines an electrical or physical layer (PHY) that supports unidirectional, point-to-point, serial coded data rates from 312.5 Mbps to 3.125 Gbps between data converters and a logic device (FPGA, ASIC, microprocessor or DSP) separated by up 20 cm of standard FR-4 (FR402/4000-2 and FR406/4000-6) printed circuit board material.  The data converters and logic devices may be connected across a backplane using one or more impedance-controlled connectors or one or more cables.

The JESD204A PHY specification is similar to the OIF (Optical Internetworking Forum) SxI-5 and TFI-5 Implementation Agreements, generally referred to commercially as Current Mode Logic (CML). Compliant transmitters (TX) and receivers (RX) are expected to achieve Bit Error Rates (BER) of less than 1e-12.  For reference, see OIF-TFI-5-01.0, TDM Fabric to Framer Interface Implementation Agreement (Optical Internetworking Forum, September 16, 2003)  and OIF-SxI-5-01.0, System Interface Level 5 (SxI-5): Common Electrical Characteristics for 2.488 –3.125Gbps Parallel Interfaces (Optical Internetworking Forum, October 2002).

The JESD204B draft specification additionally defines the OIF Common Electrical Interface (CEI) LV-6G-SR (Short Reach) as the 6.25 Gbps PHY (from 312.5 Mbps to 6.375 Gbps), and the OIF CEI-11G-SR as the 12.5 Gbps PHY.  Note that LV-6G-SR compliant transmitters and receivers are expected to achieve BER of less than 1e-15. For reference, see:  https://www.oiforum.com/public/documents/OIF_CEI_02.0.pdf

Typically, TX pre-emphasis and RX equalization (EQ) on the converters and FPGAs/ASICs is an option at 12.5 Gbps, depending on the length of the transmission line. JESD204B retains the 20 cm “reach” (length) plus one or more impedance-controlled (100 ohm differential) connectors transmission line characteristics as JESD204A.  High quality PCB material such FR-4 Nelco 4000-13SI is also potentially necessary at 12.5 Gbps, again depending on the reach of the transmission line (transmission lines are called data “lanes” in JESD204A/B).  Lanes less than 20 cm in length may not require TX pre-emphasis and RX EQ. (Altera Corporation has information on its website relating to TX pre-emphasis and RX EQ.)

Like JESD204A, 8B/10B is the coding scheme for JESD204B.  Generally speaking, more efficient coders, such as 64B/65B, are used at higher line frequencies; however, it was considered “out of scope” to redefine the coding scheme for JESD204B by the JEDEC 150.01 Task Group.  If there is sufficient industry interest, the coding scheme could be redefined as part of a future JESD204C revision.

The JESD204B specification includes new channel models for the 12.5 Gbps PHY, specified as frequency-dependent Insertion Loss Deviation (ILD) masks required for 20 cm FR-4 (FR402/4000-2 and FR406/4000-6) and one or more impedance-controlled connectors or cables.  Note that JESD204A specifies insertion loss more simply: the total insertion loss shall not exceed 6 dB from DC to 0.75 times the utilized baud rate.

JESD204A specifies TX and RX return loss (both single-ended and differential) with a single number: 7.5 dB minimum for TX; and 10 dB minimum for RX.  In the JESD204B spec, the transmitter differential output return loss minimum (from 100 MHz to 0.75 times the utilized baud rate) is 8 dB, and the common mode return loss minimum (from 100 MHz to 0.75 times the utilized baud rate) is 6 dB.  The receiver return loss minimums are the same.

JESD204A defines total jitter (TJ) as the sum of deterministic jitter (DJ) plus random jitter (RJ), measured in peak-to-peak normalized bit times or “unit intervals”.  In JESD204A with the 3.125 Gbps PHY, transmitter TJ = 0.35 p-p UI, DJ = 0.17 p-p UI and RJ = 0.08 UI p-p, where UI ranges from 3,200 psec to 320 psec.  The receiver TJ = 0.56 p-p UI, DJ = 0.32 p-p UI and RJ = 0.24 p-p UI over the same range of UI.  In the JESD204B specification, total jitter is defined the same way.

Deterministic Latency – Three New Device Subclasses in JESD204B
In the context of JESD204B, deterministic latency is measured from the parallel frame-based data input of a TX device (typically an ADC), to the parallel frame-based data output of an RX device (typically a DAC), measured within the frame clock domain.  JESD204B latency is defined (and is programmable) in units of frame clock cycles or periods.  The latency must be precisely repeatable from power-up cycle to power-up cycle, and across link resynchronization events.

JESD204B defines three normative Device Subclasses with respect to Deterministic Latency / Harmonic Clocking (DLHC):

Device Subclass 0 has no support for deterministic latency.

Device Subclass 1 defines a new source-synchronous “SYSREF signaling” high-resolution timing (deterministic up to approximately 2 GHz sample clock frequencies) DLHC protocol, with either a periodic SYSREF, a one-shot (strobe-type) SYSREF or a “gapped periodic” SYSREF distributed to all ADCs/DACs and ASIC/FPGA logic devices.  The SYSREF signal synchronizes system-wide the local TX and RX frame and multi-frame counters/dividers and the reading of RX FIFO output buffers in JESD204B.

Device Subclass 2 uses the legacy SYNC~ signal, but in a system-synchronous “SYNC~ sampling” low-resolution timing DLHC protocol.  This provides accurate deterministic latency up to approximately 500 MHz sample frequencies, utilizing SYNC~ de-assertion to phase adjust ADC, DAC and logic device frame clock and multi-frame clock counters/dividers (combined with control interface based triggering).  The SYNC~ signal conveys interface latency timing information in JESD204B, from the receiver back to the transmitter.

JESD204B defines new physical clock signals:

Device Clock = A global master clock signal synthesized by a system clock generator circuit from which all TX and RX devices (data converters and logic devices) generate their internal frame clock and multi-frame clock signals.  The device clock period is the absolute timing reference in a JESD204B system.  Note that the device clock signal can be a harmonic multiple of the frame clock; this relates directly to the Harmonic Clocking feature of JESD204B.

SYSREF = A “global” timing reference signal that can be periodic, one-shot (strobe type), or “gapped” periodic and is used to align frame clock and Local Multi-Frame Clock (LMFC) boundaries.  SYSREF is an active high signal that is sampled by the rising edge of the device clock.  SYSREF is only used in Device Subclass 1 systems. The SYSREF source must be the same as the device clock source, typically a crystal oscillator time base (such as a low jitter TCXO or VCO/PLL)

It is helpful to recall the definition of frame, multi-frame and LMFC from the JEDEC JESD204A specification:

Frame = A set of consecutive octets in which the position of each octet can be identified by reference to a frame alignment signal.

Multi-frame = A set of consecutive frames in which the position of each frame can be identified by
reference to a multi-frame alignment signal.

LMFC = Local Multi-Frame Clock.

Harmonic Frame Clocking Simplifies the PCB-Level Clock Synthesis and Distribution Challenge
Simply put, harmonic clocking allows the use of, for example, 2x, 3x, 4x, 5x, 6x, 7x or 8x FS device clock as the only PCB-level data converter clock, without the need for an additional FS-based frame clock.  [The recovered clock from the JESD204B differential input data lane signals is used as the data interface "bit clock".]  With harmonic clocking (or single clock system architecture) TX and RX devices can generate all internal clocks from a single clock source, provided that the single clock source is a harmonic multiple of the frame clock.

As a practical example, in the case of a high-speed interpolating DAC architecture (assuming an internal PLL is not used), it is typically required to generate a high-quality device clock signal that is 2x, 4x, or 8x the input data rate sample frequency.  This same 2x, 4x, or 8x clock can then be used as the device clock for the ADC, where it is internally divided to create the sample clock (FS) and frame clock.

The advantages of single clock system architectures include reduced IC package pin count and lower risk of detrimental clock feed-through (or crosstalk) effects.  In general, fewer clocks on the system PCB level reduce the potential for the disturbance of the ADC and DAC analog performance.  On the system PCB level, the design engineer has only one data conversion clock to synthesize and distribute.

Unique System Value Enhancements from JESD204A/B
The new JEDEC JESD204A/B data converter interface definition has numerous system-level technical and commercial merits:

  • Simplified PCB layout and routing, with the potential for PCB cost reduction (fewer signal layers, smaller PCB form factor, no data lane-to-clock skew management)
  • Data converter and FPGA or ASIC pin count reduction, enabling higher channel count per FPGA or ASIC, with the potential for BOM cost reduction
  • Increased system performance, enabling higher bandwidth digital signals over fewer PCB traces
  • 8B/10B PHY is compatible with fibre optic signalling for long reach applications
  • EMI/RFI radiation reduction, with the potential for easier device compliance test approval
  • Reduced signal skew management, with the potential for reduced engineering development cost
  • No PCB redesign for data converter resolution changes (12-bit to 16-bit), only FPGA logic reconfiguration / recoding, with the potential for reduced engineering development cost and faster end-product qualification.
  • Single bit error detection, by virtue of 8B/10B coding, with the potential for increased system reliability
  • Multiple time-aligned and phase coherent data converter channels for system designs such as LTE MIMO base stations, with the potential for simplified system design and reduced engineering development cost
  • Interoperability with SERDES-based FPGAs, with the major vendors offering compliant IP for their latest cost-effective programmable logic products
  • Periodic frame alignment monitoring with the potential to maintain frame alignment without data loss for system reliability and robustness
  • Optional data and control symbol scrambling to produce data independence across the JESD204A/B link, with the potential to reduce non-harmonic spurs in the data converter analog domain
  • Optional embedded Pseudo Random Bit Sequence (PRBS) generation (TX) and checking (RX) for simplified board-level Built-In Self Test (BIST)
  • Elimination of CMOS parallel bus buffers, with BOM reduced and schematic/layout simplification


Exciting Backwards-Compatible Future Path
As base station and other data acquisition and signal synthesis equipment designers drive relentlessly toward lower capital and operating expense goals, JESD204A interface high-speed data converters can help meet those goals.  With the enhancements offered by JESD204B, system designers can save even more in the critical metrics of “dollars, watts and square inches,” making this new data converter and logic device digital interface more compelling than ever.  With the expected availability of JESD204B data converters in 2H2011, the widespread adoption of this interface in 2012 seems to be assured.

About the Author
Maury Wood is General Manager of the High Speed Converters product line at NXP Semiconductors. Maury served as JEDEC JC-16 JESD204B Task Group Committee Chairman.  He has worked in the semiconductor business for more than 20 years, and previously held marketing and application engineering positions at Analog Devices and Cypress Semiconductor.

References

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