Cadence expands system and SoC verification offerings to accelerate system integration and reduce time to market

Cadence expands system and SoC verification offerings to accelerate system integration and reduce time to market

Technology News |
Cadence Design Systems, Inc. is releasing a new in-circuit acceleration based on the Incisive and Palladium XP platforms for the company’s System Development Suite.
By eeNews Europe


Extensions to the Verification IP Catalog for acceleration and emulation will give engineers the ability to go beyond simulation to speed verification of large-scale SoCs, sub-systems and systems.

“The inefficiencies and performance limitations introduced by traditionally disconnected development platforms combined with verification IP applicability being limited to simulation-only approaches are posing a threat to customers designing systems and SoCs for consumer and wireless electronics being able to deliver products on time,” said Nimish Modi, senior vice president, System and Software Realization Group at Cadence. “With the new in-circuit acceleration deliverables in the System Development Suite and the extension our Verification IP Catalog to acceleration and emulation, Cadence is taking another significant step forward towards its vision to enable open, connected and scalable system-level development.”

The effort and cost associated with utilizing different, disconnected engines for virtual prototyping, RTL simulation, acceleration, emulation, and FPGA-based prototyping pose key challenges to delivering products on time. Expanding upon its in-circuit emulation technology leadership and the industry’s only integrated simulation-acceleration and emulation environment, Cadence now offers as part of the System Development Suite a single heterogeneous environment for system-level verification based on the Incisive and Palladium XP platforms, which enables designers to leverage both the high speed and real-world interfaces of traditional in-circuit emulation environments combined with the advanced analysis capabilities available in RTL simulation. Design teams are no longer forced to create and maintain both environments, spend unnecessary time and effort to reproduce bugs, or remodel all system components targeted for one environment – tasks which are not time effective and make sub-optimal use of the existing IP assets.

New in-circuit acceleration enables teams for simulation acceleration and emulation to deploy a common unified verification environment, resulting in up-to-10x increased efficiency during system-level validation and root cause analysis. It further shortens system and SoC development times by delivering an optimal blend of performance and accuracy and optimal leverage of existing IP assets.

“Using In-Circuit Acceleration, we’ve enabled a new paradigm of system-level debug productivity while maintaining full In-Circuit Emulation performance,” said Alex Starr, emulation architect at Advanced Micro Devices. “We have reduced the time to closure on difficult, long running workloads, which enables us to increase our hardware and software coverage while reducing the overall test plan execution time.”

Universal Verification Model (UVM)-compatible Accelerated VIP enables users to smoothly transition from simulation to acceleration, in-circuit acceleration, and in-circuit emulation, giving them the ability to verify complex Systems and SoCs that are simply too large for effective verification using traditional RTL simulation.

The Cadence VIP catalog now includes Accelerated VIP for the following interface standards: ARM’s AMBA AXI 3/4 and ACE, PCI Express 2.0/3.0, USB 3.0, 10Gb Ethernet, SATA 3, and HDMI 1.4.

According to Brian Bailey, Chairman of Accellera’s Interfaces Technical Committee, “The SCE-MI standard was developed in large part because large scale designs commonly exceed the ability of simulation to verify the RTL in a timely manner. This is occurring in a greater percentage of designs today. In other words, verification acceleration has become a necessity and SCE-MI was created to provide a standard for how verification acceleration can be integrated into the flow.” Bailey continued, “The need to perform accelerated verification using a hardware based computing platform together with accelerated VIP has only grown since SCE-MI was introduced.”

Visit Cadence at

Linked Articles
eeNews Analog