ChipFlow aims for open-source chip design platform

ChipFlow aims for open-source chip design platform

Business news |
UK startup ChipFlow is developing an integrated circuit design platform with open-source EDA software writes Peter Clarke. The company was founded in Cambridge in April 2021 and says it plans to use the open-source hardware ecosystem to deliver a chip design service. This will be aimed at helping product companies…
By Peter Clarke

Share:

UK startup ChipFlow is developing an integrated circuit design platform with open-source EDA software writes Peter Clarke.

The company was founded in Cambridge in April 2021 and says it plans to use the open-source hardware ecosystem to deliver a chip design service. This will be aimed at helping product companies design and order up their own chips. ChipFlow is in the process of raising a £2 million seed round of financing.

The plan is to use a Python-based hardware description language and a library of reusable modules and standard cells to help customers design their own chips. The platform will include automated IC layout using artificial intelligence as well as automated consignment to manufacturing and shipping, optimized for low volumes.

The company was founded by CEO Rob Taylor who has 20 years experience commercializing open-source software.

The company’s CTO is Staf Verhaegen, a prominent developer of open-source EDA and open-source hardware. Verhaegen spent 23 years with the IMEC research institute prior to co-founding ChipFlow.

The company has numerous links back to the Free and Open Source Silicon (FOSSi) Foundation

Olaf Kindgren, a director of FOSSI, is listed on the ChipFlow team. Kindgren became involved in FOSSI through the OpenRISC project in 2011 and he is the maintainer of FuseSoc, a package manager and set of build tools for hardware description language code.

Ian Page, an Oxford-based academic and venture capital manager, who worked on the compilation of software down to FPGA implementation in the 1990s is listed as co-founder and part-time advisor to the company.

Taylor told eeNews Analog that the offering would essentially support digital design to begin with some analog options. The offering is by way of a cloud platform where users will have access to open-source design tools, such as Coriolis place and route and Amaranth HDL front-end. “The customer shouldn’t need to go the physical design,” said Taylor.

The business model is that ChipFlow hosts the platform in the cloud to support the design, and adds value by collecting multiple IC designs for manufacture on multi-project wafers run by cooperating silicon foundries. Taylor declined to say exactly which manufacturing processes would be supported. He said the company has already gained experience with SkyWater 130nm process and with a couple of TSMC processes.

ChipFlow plans to start well behind the expensive leading-edge of chip manufacturing. It states that greater than 80 percent of product needs can be fulfilled in the most cost-efficient way by using manufacturing processes that are more than 10 years old.

However, over time it expects to broaden its technology offering. The company has published a road-map that will see its platform enabling high-performance designs by 4Q24.

The company said it reached first revenue in 3Q21 and is now focusing on a limited range of designs. “We’ve got four tape-outs; mainly microcontroller designs,” Taylor said.

www.chipflow.iowww.fossi-foundation.org

News articles:

Linked Articles
eeNews Analog
10s