Dedicated EDA retime model optimises chip-to-chip link design

Dedicated EDA retime model optimises chip-to-chip link design

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Agilent Technologies' retimer solution is the company’s latest addition to its repeater model library for quickly and accurately solving the challenge posed by signal distortion in the multigigabit-per-second regime.
By eeNews Europe

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The retimer solution, available in the Advanced Design System 2013, Transient Convolution Element and SystemVue 2013 AMI Modeling Kit, is used for designing electrical retimers in chip-to-chip, high-speed digital links. Before the multigigabit era, chip-to-chip digital signals propagated across entire printed circuit boards with little distortion. However, at today’s speeds, rising and falling edges degrade after traveling only a few inches on production board materials like FR4. In digital applications, it is cost-prohibitive to use high-frequency laminate board materials to solve the problem. A more economical solution is to insert a mid-channel retimer circuit.

Up to now, simulation tools used to design in these nonlinear devices have used computationally expensive SPICE techniques like Newton-Raphson iteration on modified nodal analysis of Kirchoff’s current law. With this latest breakthrough, Agilent offers a quick solution based on bit-by-bit channel simulation and the IBIS AMI flow to retimer applications. Unlike SPICE, these techniques include computationally efficient algorithms like superposition. Using a prestandard, novel extension to the industry-standard IBIS AMI flow, SystemVue 2013 now offers model builders (typically integrated circuit vendors) a tool to build retimer models. The models run in ADS, the tool that IC consumers (typically data center and telecoms equipment manufacturers) use to design these chips into their systems.

Visit Agilent EEsof EDA Software at www.agilent.com/find/eesof

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