Family of singal processing cores for video enhancement

Family of singal processing cores for video enhancement

New Products |
UK signal processing experts RFEL is extending its military designs into the industrial market with a new family of Video Processing IP cores.
By eeNews Europe

Share:

High quality video processing have always been in demand for military and security surveillance and targeting systems. Such systems require high resolutions, high frame-rates, ultra-low latency and mission-flexibility through provision of live re-programmability. For example, video must be enhanced, rotated or similarly corrected in real-time; In software based solutions, this can often take a lot of power and, crucially, time. Conversely, a wholly custom hardware solution lacks adaptability and intelligence. RFEL has proven that FPGAs are a perfect platform to create solutions that meet the user’s demanding requirements with RFEL’s flexible and deterministic FPGA IP core building blocks. The IP FPGA cores can be supplied with standard software interface frameworks to simplify their deployment and RFEL can modify the cores if required to meet the requirements of constrained resources or legacy platforms.

"For the past 12 years, we have built our expertise in Digital Signal Processing and created award-winning solutions for RF on FPGAs," said Dr Alex Kuhrt, RFEL’s CEO. "We have found that there is a lot of common ground with processing video and so we have been able to leverage our libraries of proven IP cores to rapidly create a new family of Video Processing cores. These are available now, either as standalone cores or as part of a system solution created by our Design Services team to meet a customer’s requirements, which we find are increasingly for a complete product."

A Digital Rotation core supersedes mechanical rotation hardware with state of the art digital processing. Many of the digital rotation IP core features can be configured while the system is still running, so that the user is always fully in control. Reliable, maintenance-free and targeted to low-cost FPGA devices, the digital rotation IP core is a highly efficient, arbitrary sub-degree angle, real-time, 360 degree rotation engine.

The Digital Re-sizing and Digital Zoom (DZ) core far exceeds the efficiency and reliability of software-based, image magnification solutions, manipulating images at exceptional speed but consuming a fraction of the power. High-performance image processing systems can now crop and enlarge dynamically and adaptive video systems can now zoom quickly and effectively.

An Image Enhancement core provides a range of advanced image enhancement processing functions such as noise reduction, correction of image distortion and contrast enhancement. User interface displays can be realised with configurable full graphic or symbolic overlays.

Motion Stabilisation is an example of a complex and high performance IP core. Stabilisation is performed in real-time and entirely electronically. The algorithm compensates for overall x-y shift and roll of a scene, improving end-user vision and reducing work-load (see picture). Object tracking may be improved in certain down-stream tracking applications. Highly resource efficient and very low power variants of the stabilisation product are available. There are also more complex adaptive system configurations that can be tailored to the specific performance requirements of an application. These embedded software elements are closely coupled to the FPGA functions and typically produced as system-on-module designs.

www.rfel.com

Linked Articles
eeNews Analog
10s