Fujitsu standardizes on Cadence DFM technologies for 28-nm ASIC and mixed-signal designs

Fujitsu standardizes on Cadence DFM technologies for 28-nm ASIC and mixed-signal designs

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Fujitsu Semiconductor Limited has adopted Cadence signoff design-for-manufacturing (DFM) technologies for the company’s complex 28-nm ASIC and system-on-chip (SoC) mixed-signal designs. Deploying the Cadence DFM offerings is helping Fujitsu Semiconductor engineers ensure high yield, predictability, and a faster path to Silicon Realization for next-generation chips that will serve as the brains of the company’s advanced consumer electronics.
By eeNews Europe


The Cadence end-to-end digital and analog flows for Silicon Realization deliver DFM in-design technology within the Virtuoso custom/analog and Encounter digital flows.

“After an extensive evaluation of all vendors in the market, we selected the complete Cadence DFM set of technologies for our most advanced ASIC and SoC designs,” said Hiroshi Ikeda, director of the System LSI Technology and Design Platform Development Department at Fujitsu Semiconductor Limited. “The production-proven DFM technology gives us confidence in our ability to manage the complexity of advanced 28-nanometer effects in the fastest turnaround time, with the highest quality of silicon. Also, the seamless integration into the Cadence Virtuoso and Encounter flows makes it very straightforward for our design teams to adopt and fully leverage in their day-to-day work.”

Following comprehensive benchmarking, Fujitsu Semiconductor selected the Cadence Litho Physical Analyzer, Cadence CMP Predictor and Cadence Litho Electrical Analyzer for 28-nm in-design physical signoff and variability optimization for its ASIC and SoC designs.

As process geometries shrink beyond 28-nm, the Cadence DFM technologies enable Fujitsu Semiconductor to tackle the essential tasks of accurately modeling and predicting the impact of physical and electrical variability (layout dependent effects) on the yield and performance of a chip. Cadence in-design DFM signoff tools enable engineers to analyze these impacts, and fix problems, during digital and custom design implementation, rather than the traditional – and more costly and risky – route of addressing DFM signoff checks after the design is completed and ready to tape out.

The Cadence Litho Physical Analyzer applies proprietary, foundational algorithms to provide near-linear scalability, thereby providing blazing fast silicon convergence. The Cadence CMP Predictor allows Fujitsu Semiconductor engineers to detect topography variations of their manufacturing process early on via extensive simulations. Fujitsu Semiconductor design teams use the Cadence Litho Electrical Analyzer to identify and optimize their libraries for layout-dependent effect variability early on, therefore ensuring that their design meets their planned performance metrics.

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