Google, AMD tipped as early adopters of TSMC chiplet manufacturing

Google, AMD tipped as early adopters of TSMC chiplet manufacturing
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Google and Advanced Micro Devices (AMD) will be among the first companies to use a chiplet-style assembly technology being offered by foundry TSMC, according to reports.
By Peter Clarke

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The first SoIC chiplets are expected to enter mass production in 2022. Google’s interest is in autonomous driver assistance systems (ADAS), according to a Nikkei report. AMD would create closely-coupled processor and memory systems to gain competitive advantage against Intel in the data center.

TSMC has introduced a service it calls 3DFabric that comprises a family of 3D silicon stacking and packaging technologies. It includes the established CoWoS and InFO packaging styles, which were used for die-to-die and die-to-interposer packaging. Xilinx was an early adopter of CoWoS. 3DFabric also adds a third tier that TSMC calls SoIC for System on Integrated Chips (SoIC).

SoIC broadens the ability to stack die-to-die with high-density vertical stacking and minimum resistance, inductance and capacitance in the interconnect. This translates into an ability to stack and link different types of known-good-die, such as processors, memory, sensors and passives into a single packaged component allows the use of multiple manufacturing processes that are best in class for a particular function and reduces interconnect and power consumption.

It has implications for electronic design automation (EDA) which becomes a 3D rather than a 2D task and for design partition. It also has implications for the semiconductor supply chain where foundries have previously focused on front-end processing and a set of back-end service providers performed assembly and test services. TSMC, already the world’s largest foundry and most valuable chip company, will be taking on both roles for some customers who use its leading-edge processes.

Next: TSMC does the packaging


To support its move TSMC has been planning an IC packaging and testing plant in Miaoli, northern Taiwan. The spending attributed to the plant is NT$300 billion (about $10 billion), an unusually large amount but one consistent with the blurring of the lines between front-end and back-end processing associated with chiplet-style manufacturing.

The plant is scheduled to be completed in May 2021 with operations set to start in mid-2021, the reports state.

TSMC has created a set of web pages to explain its 3DFabric offering at https://3DFabric.tsmc.com.

Other reports have said that TSMC has put in an order for 13 extreme ultraviolet (EUV) lithography machines to ASML Lithography Holding NV seeking to boost its manufacturing capacity for 7nm and 5nm processes in 2021 and 2022. Such machines typically priced at around $100 million each.

Related links and articles:

www.tsmc.com

https://3DFabric.tsmc.com

News articles:

Chiplet-savvy TSMC to build $10 billion assembly and test plant

TSMC becomes world’s biggest chip company

Intel teams with Leti to advance 3D packaging

TSMC preps for ‘chiplet’ style manufacturing in 2021

Intel, Samsung, TSMC to drive chip packaging forward

Birth of chiplet market shows more than 40% annual growth

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