HEVC decoder silicon IP now with 10-bit support for high resolution video
Requirement of TV broadcasting for carrying 4K and ultra-high definition content is now driving the adoption of the HEVC (High Efficiency Video Coding) standard. This demand for devices supporting HEVC is growing fast, and Allegro DVT is ready with what the company claims to be the industry’s first fully compliant HEVC decoding IP that supports both Main and Main10 profiles. The Main10 profile was specifically designed to improve 4K content video quality thanks to 10-bit colour depth support.
The HEVC Decoding IP runs real-time on FPGA and can be immediately delivered to any customer wishing for 4K enabled products. It is expected that 4K content will drive the market of next-generation ultra HD television displays (UHDTV) and content capture systems.
One of the major innovations in the HEVC standard, is the introduction of several tools to parallelize processing, such as “dependent slices”, “tiles” and “wavefront parallel processing”. Allegro’s HEVC Decoding IP is based on a scalable and unique multi-core architecture, supporting any combination of these parallel processing tools. This unique decoder architecture removes all constraints on the encoders and ensures interoperability with all types of parallelized encoding.
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