The technical program for this year’s IEDM has been posted with theme to reflect two industry trends: the use of so-called 2D materials – having thicknesses measured in atoms –  in order to further miniaturize transistors; and the use of a variety of 3D architectures to incorporate more features and performance from transistors and circuits.

After a virtual event in 2020 due to the Covid-19 pandemic the 67th IEDM returns to being an in-person event. It is due to be held December 11 to 15, 2021 at the Hilton San Francisco Union Square hotel.

A team from IBM and Samsung have built vertical CMOS devices using so-called vertical transport nanosheet field effect transistors (VTFETs) on bulk silicon. The vertical devices offer the opportunity for continued scaling beyond what is possible in horizontal transistor manufacturing. This is because the gate length and spacer size – two elements that determine gate pitch (the distance between transistors) – can be optimized in ways that aren’t possible horizontally.

The VTFETs also promise excellent voltage and drive current as a result of reduced parasitic losses compared with laterals designs.

The researchers made functional ring oscillators as test circuits, which showed about a 50 percent reduction in capacitance versus lateral design reference. (Paper #26.1, “Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices,” H. Jagannathan et al., IBM/Samsung).

Researchers from Belgian Research institute IMEC usually author many papers at IEDM and this year of particular note is a paper on a concept that has been in development at IMEC for several years – that of moving power rails to beneath the transistor plane

Separating power and logic interconnect should bring the benefit of reducing interconnect complexity and allowing smaller chip designs. The researchers drawn from IMEC and ASM International have experimented with different metals both for the buried power rail (BPR) and for low-resistence contacts needed between the BPR and the through-silicon-vias that take power out to the chip surface. The research indicates that for 3nm transistors tungsten optimizes both the line and the contect resistance but that for 2nm and 1nm nodes molybdenum is better for the BPR and ruthenium for the via contacts. (Paper# 22.5, “Buried Power Rail Metal Exploration Towards the 1nm Node,” A. Gupta et al, IMEC/ASM International).

Samsung is set to present a paper on the improved reliability of DRAM made at the 15nm to 17nm nodes compared with 18nm node, achieved by transitioning to extreme ultraviolet (EUV) lithography for critical layers instead of using ArF immersion lithography.

Samsung researchers will present a comprehensive paper detailing dramatic improvements in DRAM reliability at the 17nm-to-15nm technology nodes vs. the 18nm node. This was achieved by transitioning to EUV for critical layers instead of using ArF immersion lithography. High Temperature Operation Life (HTOL) testing exhibited a 2.2x reduction in failure rates for the 17nm and 15nm nodes. (Paper #6.6, “Reliability Characterization for Advanced DRAM using HK/MG + EUV Process Technology,” S. Lee et al., Samsung).

Interestingly Samsung has already started to ship 14nm DDR5 DRAMs made using a 14nm manufacturing process and five layers of EUV lithography (see Samsung starts mass production of 14nm EUV DDR5 DRAM).

Ferroelectric memory was a prominent topic at last year’s virtual IEDM and in 2021 Intel researchers are due to present a paper on embedded FeRAM made hafnium. The FeRAMs are based on deep-trench antiferroelectric (AFE) capacitors.

The researchers will describe how they built FeRAM with deep-trench AFE capacitors that showed industry-leading performance (read/write speed of ~2ns) and reliability (endurance >1012 cycles), with high levels of uniformity at the 300mm wafer scale. The devices showed industry-leading performance (read/write speed of approximately 2ns) and endurance of greater than 1012 cycles. (Paper #33.2, “FeRAM using Anti-ferroelectric Capacitors for High-speed and High-density Embedded Memory,” S. -C. Chang et al, Intel).

Links to the full program can be found at the IEEE-IEDM website.

Related links and articles:

News articles:

Buried power rail takes transistors to 2nm

IMEC, ferroelectrics prominent in virtual IEDM program

Samsung starts mass production of 14nm EUV DDR5 DRAM

Backside of the wafer promises 3D chip improvements

Here comes the forksheet transistor, says IMEC


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