Imec and Renesas Electronics reveal world’s first multi-standard RF receiver in 28nm CMOS
The 28nm receiver is a linear software-defined radio (SDR) operating from 400MHz up to 6GHz and supporting reconfigurable RF channel bandwidths up to 100MHz. Through novel design and architecture techniques, the receiver operates at a low standard supply of 0.9V, while maintaining +5dBm of out-of-band IIP3 and tolerating 0dBm blockers. It achieves noise figures down to 1.8dB, occupies an active area of 0.6mm2, and consumes less than 40mW.
The ADC is a 410MS/s dynamic 11bit pipelined SAR ADC in 28nm CMOS. It achieves a peak Signal-to-Noise Distortion Ratio (SNDR) of 59.8dB at 410MS/s with a power consumption of 2mW. By combining novel digital calibration techniques with a new ADC architecture, an excellent energy efficiency was achieved. The ADC, including an on-chip calibration engine, occupies an active area of 0.11mm2.
“High level integration and low power are strongly required for recent wireless transceivers. There is every possibility of creating epoch-making architecture for RF and analog cores by using fine CMOS technology,” said Hisayasu Sato, Senior Manager of 2nd Analog Core Development Department, Core Technology Business Division, 1st Solution Business Unit, Renesas Electronics Corporation. “Through the collaboration with imec, we have been developing cutting-edge technologies. We continue to supply competitive IP cores and solutions to our customers.”
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