In an online presentation called ‘Intel Accelerated,’ the major element was renaming its future manufacturing process nodes and a new transistor architecture due for introduction at the 2nm stage. The transistor format, a refinement of the FinFET, is called RibbonFET and is accompanied by backside power supply named PowerVia.

The renaming starts with what was 10nm FinFET super enhanced becoming 7 and what was 7nm becomes 4 and so on. This makes Intel appear to be in a closer competitive position with rival semiconductor companies TSMC and Samsung, after Intel had stalled for several years while trying to achieve reasonable yields at 10nm.

Whether the naming convention is accurate is moot as the node names for chip manufacturing companies long ago ceased to refer to any direct minimum dimension in their naming conventions. There has been discussion for many years that Intel’s 10nm was roughly equivalent to 7nm from TSMC.

Production on 7 is due in 1Q22; production on 4 some time in 2023; the 3 process is timetabled to begin before the end of 2023. Intel’s 20A process is expected to ramp in 2024 and will be the point at which RibbonFET and PowerVia will be introduced fully into production. Gelsinger made the point that elements of new transistor architecture will be investigated at earlier nodes and EUV will be deployed across increasing numbers of metal layers as Intel makes its way along the roadmap.

The A in the 20A and an 18A process that follows stands for angstrom, which is equivalent to 0.1nm. The Intel 18A process is already in development for early 2025 with refinements to RibbonFET that will deliver another increase in transistor performance.

However, the rebooting of Intel by way of node renaming is for now only a marketing exercise. Intel has to execute on the roadmap if it is to fulfil Gelsinger’s promise of getting the company back on top as a leading semiconductor company. And Intel’s struggles have resulted in the near-term measure of it requiring the support of foundry rival TSMC over several production nodes (see Report: Apple, Intel are first to adopt TSMC’s 3nm process).

Next: What is so special about a name?

Gelsinger said the renaming of the roadmap brought clarity that was essential to its Intel Foundry Services (IFS) business. “The interest in IFS has been strong and I’m thrilled that today we announced our first two major customers. IFS is off to the races!” Intel announced Amazon and Qualcomm as its first two IFS customers but Gelsinger had previously been reported saying the company is talking to 100 potential customers. Qualcomm is set to be a lead partner on the 20A manufacturing process.

However, much of the now renamed roadmap is already ‘baked-in’ to Intel’s near-term future and is essentially a road it must travel along faster than the competition if it is to catch up. Intel said it was planning for swift adoption of next-generation extreme ultraviolet lithography (EUV), referred to as high numerical aperture (High NA) EUV and that it is set to receive the first High NA EUV production tool in the industry from manufacturer ASML Holding NV.

Ribbon and Power

Hence, much of the interest in the technology presentation was in the transistor announcement

However, this architecture is familiar stuff being Intel’s interpretation of gate-all-around (GAA) nanosheet transistor ideas offered up by IMEC research institute over the last several years. Similarly IMEC first proposed the idea of the buried power rails for high density logic. Nonetheless Intel will be migrating to nanosheet transistors at a later node than its competition. Samsung first reported on nanosheet transistors in its 3nm manufacturing process in 2018 and has now released a physical design kit to enable designers to work with the process (see Samsung releases PDK for 3nm gate-all-around processes).

Intel proclaimed the advantages of RibbonFET and PowerVia by way of vague ‘hand-waving’ arguments. There are performance-per-watt increases of 10 to 20 percent from one node to the next but these were only expressed in these relative terms. On introduction the RibbonFET will allow yet faster switching, higher drive current density by way of the stacking of the ribbons and different drive currents by way of the width of ribbons, Intel said.

Next: Chiplets coming

Similarly PowerVia uses up to vias 500x smaller than those conventionally used in packaging and the separation of signal above and power below increases attainable frequencies of operation and reduces power leakage, the company said.

There was no discussion of materials for inclusion in the transistor channel. Silicon-germanium and strain engineering works there but there is plenty of research into the use of additives and the opportunities for carbon, graphene and other 2D semiconductor material systems.

There are also plenty of IMEC-proposed refinements to come, including forksheet transistors and stacked complementary transistors for efficient and dense CMOS logic.


Elsewhere in the presentation Intel spoke of 3D packaging with the announcement of Foveros Omni and Foveros Direct.

Foveros Omni effectively launches ‘chiplet’ style component assembly with its support for die disaggregation by mixing multiple top die tiles with multiple base tiles across mixed fab nodes. Intel said it is expected to be ready for volume manufacturing in 2023.

Foveros Direct adds the refinement of direct copper-to-copper bonding for low-resistance interconnects and blurs the boundary between where the wafer ends and where the package begins. Foveros Direct enables bump pitches below 10 micron, providing an order of magnitude increase in the interconnect density for 3D stacking, opening new concepts for functional die partitioning that were previously unachievable. Foveros Direct is complementary to Foveros Omni and is also expected to be ready in 2023.

Intel is planning an event called InnovatiON due to take place in San Francisco and online October 27 and 28

Related links and articles:

News articles:

Here comes the forksheet transistor, says IMEC

Backside power opens up new realms in chip design

Samsung releases PDK for 3nm gate-all-around processes

IEDM: Samsung makes 3nm gate-all-around CMOS


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