The part is based on a triple-level cell (TLC) with replacement gate and charge-trap storage technology and components are now shipping to customers from Micron’s wafer fab in Singapore. These customers include Micron’s in-house brand of solid-state drive maker Crucial.
Micron said it will introduce additional products based on the same technology during 2021. It has also said it plans to extend the number of layers in the future, presumably going to 256 layers. The memory is a 512-Gbit design made of two strings of 88-layers. The use of double strings has been proposed by Samsung to get to 160-layers (see Samsung plans to ‘double-stack’ 3D-NAND flash memory).
Micron said the 176-layer 3D-NAND has a 35 percent improved read and write latency compared with the company’s previous generation of high-volume 3D-NAND.
The data rate of the device is 1.6 gigatransfers per second on the Open NAND Flash Interface (ONFI) bus, a 33 percent improvement over the previous generation.
Micron has improved scalability and performance for future NAND generations by transitioning its NAND cell technology from floating gate to charge-trap. This charge-trap technology is combined with Micron’s replacement-gate architecture, which uses metal wordlines instead of silicon. This seems to have reduced the layer and die thickness and increasing layer count clearly can reduce die area for the same size capcity of component.
The ability to put CMOS peripheral circuity under the memory stack in an arrangement Micron calls CMOS-under-array (CuA) also helps and Micron claims it is offering 30 percent smaller die area than competitive devices.
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