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The video was available here at the time of posting and my report of the technology announcements covered is here: Intel renames manufacturing nodes, tips RibbonFET, PowerVia.

The video is led by CEO Pat Gelsinger with support from Ann Kelleher, senior vice president of technology development, and others. There’s some quantitative detail, plenty of hand-waving arguments but a technical presentation of sorts. It is also an hour of mood music to the tune of ‘Intel’s back’.

But assertions, roadmaps and enthusiasm are not achievements. Now Intel must execute on its ‘new’ roadmap faster than the competition can execute on theirs. And the competitors are already a couple of steps down the road. If Intel executes very well, it might, just might, be able to catch up with TSMC by 2025 and be a credible supplier of 2nm silicon.

Gelsinger was quite clear the company is on an annual cadence to introduce five process nodes across 4 four years. “The spirit of tik-tok is alive and well. We are just moving at a very torrid pace,” Gelsinger said. The aim is to achieve process parity in terms of performance-per-watt by 2024 and “unquestioned leadership” in 2025.

Certainly there is little point in entering a race if you do not believe you can win, but I’m doubtful that Intel can get into the leadership position. Gelsinger’s analogy was that in a bicycle race it is easier to accelerate from the number two position. Maybe, but perhaps Intel can at least stay in touch, and prevent the leading riders from breaking away.

It is what patriotic Amazon and Qualcomm are hoping will happen. These US companies have signed up as key customers to help Intel accelerate its technology journey in terms of packaging and foundry engagement.

Intel knows It needs to accelerate, hence the webcast. And Gelsinger is energetic and enthusiastic. But if wishes were horses, all would ride.

Next: Execute: Faster


Now it is about execution, something that Intel used to be very good at, but has let slip over the last decade. In the webcast Intel gave enough detail of the performance uplift between the newly-named nodes and enough timetable information that they can be held to account quite quickly.

But Gelsinger’s claims also depend on the execution of the competition. To continue Gelsinger’s analogy, TSMC is looking very easy in the saddle. The foundry leader will be confident that they can thwart Intel’s aspiration to achieve “unquestioned leadership” in semiconductor processing by 2025. From the webcast it is clear Gelsinger is hoping that closer relationships with equipment suppliers such as ASML with regard to EUV and with research groups at IBM, IMEC and Leti can help his firm move faster than the competition.

It is also what Ann Kelleher, senior vice president of technology development, must surely hope for because she has been promoted to deliver this roadmap. If Kelleher succeeds, Intel succeeds — and Qualcomm, Amazon and others have options.

If Kelleher cannot enable Intel to shake off the manufacturing funk the company has been languishing under, then Gelsinger will probably come to be seen as the last throw of the dice by a 20th century giant that was unable to adapt to the post-PC era. If she can, then Kelleher and Gelsinger just might be able to put Intel back in the race.

One thing that Intel has going for it is that there is a clear and obvious political will to have a domestic route from semiconductor R&D through leading-edge chip design and on to domestic manufacturing and packaging. And US politicians and Intel’s management fully understand the tens of billions of dollars and considerable time required to support that aspiration.

Related links and articles:

www.intel.com

News articles:

Intel renames manufacturing nodes, tips RibbonFET, PowerVia

IBM announces first 2nm chip and manufacturing process

Intel to build two wafer fabs, be foundry for Europe

Here comes the forksheet transistor, says IMEC

Backside power opens up new realms in chip design

Samsung releases PDK for 3nm gate-all-around processes

IEDM: Samsung makes 3nm gate-all-around CMOS


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