NXP expands industrial control series to support energy-efficient controls and appliances

NXP expands industrial control series to support energy-efficient controls and appliances

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The new device also expands NXP’s Cortex-M0 microcontroller offering with a wide range of Flash memory sizes. LPC1200 customers can now choose the exact Flash memory size they need, ranging from 32 KB to 128 KB in increments of 8 KB. The LPC1200 product platform is specifically designed with flexibility…
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The new device also expands NXP’s Cortex-M0 microcontroller offering with a wide range of Flash memory sizes. LPC1200 customers can now choose the exact Flash memory size they need, ranging from 32 KB to 128 KB in increments of 8 KB.

The LPC1200 product platform is specifically designed with flexibility and customization in mind, making it particularly suitable for a wide variety of energy-efficient system and power management requirements. For example, in advanced washing machines, the LPC1200 can control the motor systems, handle the user interface, monitor system power consumption, and manage off-board communications in a simple, integrated and energy-efficient solution. Its high current GPIO can directly control TRIACs without the need for external transistors, further reducing footprint and costs.

Designed for smart appliances and white goods In tomorrow’s energy-efficient smart appliance designs, the CPU will not only have to manage the user interface and control, but will also increasingly be required to drive multiple motor systems, as well as continuously measure current and voltage to calculate active power with high accuracy. The LPC1200 series meets these demanding system requirements with its high score of over 45 in CoreMark CPU performance benchmark testing, equivalent to 1.51/MHz.

For high volume applications, the LPC1200 platform can provide rapid delivery of application-specific solutions (ASSP) for a wide range of industrial control requirements, through flexible interconnections between the interrupt controller, DMA sub system, on-chip peripherals and GPIO. By recognizing external and internal events and carrying out pre-defined tasks without CPU intervention, the CPU load is dramatically reduced, allowing the CPU to remain in power down longer.

Maximizing flexibility, efficiency and robustness The NXP LPC1200 offers over 50 Flash and SRAM memory combinations, giving designers maximum flexibility to optimize the features and product cost within the same footprint. In addition, the small 512 Byte erase sector of the Flash memory brings multiple design benefits, such as finer EEPROM emulation, boot-load supports from any serial interface, and ease of in-field programming with reduced on-chip RAM buffer requirements.

Taking advantage of the ARM Cortex-M0 v6-M 16-bit Thumb instruction set, the LPC1200 has up to 50 percent higher code density compared to common 8/16-bit microcontrollers performing typical tasks. The Cortex-M0 efficiency also helps the LPC1200 achieve lower average power for similar applications. NXP’s SRAM architecture allows the LPC1200 to minimize power by automatically setting each of the 2KB low-power blocks into its lowest possible power mode.

Designed for high reliability and robustness, the LPC1200 is rated as high immunity, based on the Electrical Fast Transient (EFT) test conducted by Langer EMV-Technik GmbH per IEC61697-1 recommendations. Electrostatic Discharge (ESD) protection is rated at 8 kV.

The LPC1200 comes with a set of peripherals that are specifically suited for appliances and industrial design:

  • A Windowed Watchdog Timer with an independent internal oscillator source, designed to comply with IEC 60730 Class B safety requirements for white goods
  • A Programmable Digital Filter on all GPIO pins allowing better control of signal integrity for industrial applications
  • I2C with Fast-mode Plus feature with 10x higher bus-drive capability compared to typical I2C I/O drives, allowing for twice as many devices on the same bus, as well as longer transmission distances
  • Optimized ROM-based divide library for Cortex-M0 offering several times the arithmetic performance of software-based libraries, as well as a highly deterministic cycle time combined with reduced Flash code size
  • Dual analog comparators with 32 levels of voltage reference, edge and level detection and output feedback loop supporting multiple states, such as monostable, astable or simple set/reset

The LPC1200 extends NXP’s Cortex-M0 microcontrollers portfolio with up to 55 GPIOs, multiple timers/serial channels, and new onboard peripherals including RTC, DMA, CRC and 1 percent internal oscillator, which provides the required accuracy for Baud rate generation. Upcoming LPC1200 derivatives will also include additional features, such as an integrated 40×4 segment display driver.

Availability

The LPC1200 Industrial Control series is available now in six initial Flash sizes including 32, 48, 64, 80, 96 and 128 KB in both 48LQFP and 64LQFP packages. Devices in the same footprint share exactly the same peripheral sets and are fully pin-compatible. The integrated segment display driver option will become available in LQFP100 package in Q2.

All NXP Cortex-M microcontrollers are upwardly binary compatible and offer all the advantages of a single development toolchain. Users can easily migrate their designs between Cortex-M0 and Cortex-M3 with minimal effort. The easy-to-use LPCXpresso IDE for the LPC1200 series is priced under US $30.

NXP will showcase the LPC1200 at Embedded World in Nuremberg, Germany, March 1-3, 2011 (Booth 12-218), as part of a Smart Appliance demonstration.

More information about the LPC1200 Industrial Control Series at
ics.nxp.com/products/lpc1000/lpc12xx/

Visit NXP at www.nxp.com

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