Samsung plans to ‘double-stack’ 3D-NAND flash memory

This comes shortly after the news that Yangtze Memory Technologies Co. Ltd. (Wuhan, China) has developed a 128-layer, four-bits-per cell (QLC) 3D-NAND flash chip with a total capacity of 1.33Tbits (see China’s YMTC takes lead in 3D-NAND memory). YMTC plans to start mass-producing the memory before the end of 2020.

Now Samsung is accelerating the development of its seventh generation of what it calls vertical-NAND or V-NAND technology with 160 or more layers, according to ETNews. That would re-establish a lead over YMTC and many other flash chip manufacturers who are just bringing 112- or 128-layer chips to production this year.

ETNews reports that Samsung plans to use a “double-stack” arrangement in its seventh generation V-NAND flash memory. This technology uses twice the number of through silicon vias (TSVs) to connect the layers. This is presumably done on an odd- and even-layer basis so that electrically the 160 layers appear to be two interleaved 80-layer stacks.

There are both electrical and lithographic trade-offs to be made in 3D-NAND flash and the “double-stack” arrangement appears a neat way to keep 2D layer geometries relaxed while stacking as many memory transistors as possible, without creating read and write difficulties with long transistor chains.

NAND flash suppliers’ roadmaps 2018 to 2021. Source: TrendForce.