Samsung Electronics Co. Ltd. has announced it has started production of its 3nm process using a nanosheet gate-all-around (GAA) architecture.
The market leader in foundry chip production, Taiwan Semiconductor Manufacturing Co. Ltd. is expected to start production on its own 3nm manufacturing process later this year.
Samsung describes its approach to nanosheet transistor production as Multi-Bridge-Channel FET (MBCFET) (see Samsung 3nm designs can start on Cadence EDA tools). It improves power efficiency by reducing the supply voltage while enhancing performance by increasing drive current capability.
The company is making the first applications of the MBCFET optimized for high-performance computing and plans to expand to mobile processors where low-power optimization is more important.
“Samsung has grown rapidly as we continue to demonstrate leadership in applying next-generation technologies to manufacturing, such as foundry industry’s first high-k metal gate, FinFET, as well as EUV. We seek to continue this leadership with the world’s first 3nm process with the MBCFET,” said Siyoung Choi, head of foundry business at Samsung Electronics, in a statement.
By using sheets, rather than previous generation nanowires Samsung gains the ability to adjust the channel width to optimize for power and performance.
Samsung’s benchmarks its first-generation 3nm process – compared to its 5nm process – as being able to reduce power consumption by up to 45 percent, improve performance by 23 percent, and reduce area by 16 percent. A second-generation 3nm process is set to reduce power consumption by up to 50 percent, improve performance by 30 percent, and reduce area by 35 percent, compared with the 5nm process.
Samsung has been providing design support through its Samsung Advanced Foundry Ecosystem (SAFE) since 3Q21 by way of EDA partners Ansys, Cadence, Siemens and Synopsys.
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